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(4) Wait cancellation method
The four wait cancellation methods are as follows.
• By writing data to the IIC0 register
• By setting the IICC0.WREL0 bit (canceling wait state)
• By setting the IICC0.STT0 bit (generating start condition)
• By setting the IICC0.SPT0 bit (generating stop condition)
Note Master only
When an 8-clock wait has been selected (WTIM0 bit = 0), whether or not ACK has been generated must be
determined prior to wait cancellation.
(5) Stop condition detection
The INTIIC0 signal is generated when a stop condition is detected.
16.8 Address Match Detection Method
2
When in I
C bus mode, the master device can select a particular slave device by transmitting the corresponding
slave address.
Address match detection is performed automatically by hardware. An INTIIC0 interrupt request signal occurs when
a local address has been set to the SVA0 register and when the address set to the SVA0 register matches the slave
address sent by the master device, or when an extension code has been received.
16.9 Error Detection
2
In I
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IIC0 register
of the transmitting device, so the IIC0 register data prior to transmission can be compared with the transmitted IIC0
register data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
2
CHAPTER 16 I
C BUS
Note
Note
User's Manual U16896EJ2V0UD
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