Timer Interrupt Enable Register (Tier) - Hitachi H8/3035 Series Hardware Manual

Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1
IMFB Description
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
TCNT = GRB when GRB functions as a compare match register.
TCNT value is transferred to GRB by an input capture signal, when GRB functions
as an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0
IMFA Description
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA.
1 [Setting conditions]
TCNT = GRA when GRA functions as a compare match register.
TCNT value is transferred to GRA by an input capture signal, when GRA functions
as an input capture register.

8.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel Abbreviation Function
0 TIER0
1 TIER1
2 TIER2
3 TIER3
4 TIER4
Enables or disables interrupt requests.
(Initial value)
(Initial value)
193