Intel SE7520JR2ATAD2 Manuals

Manuals and User Guides for Intel SE7520JR2ATAD2. We have 1 Intel SE7520JR2ATAD2 manual available for free PDF download: Technical Manual

Intel SE7520JR2ATAD2 Technical Manual

Intel SE7520JR2ATAD2 Technical Manual (225 pages)

Server Board Technical Product Specification

Brand: Intel | Category: Computer Hardware | Size: 3 MB

Table of Contents

Revision History
2
Table of Contents
4
1 Introduction

19
- Chapter Outline
  19
- Server Board Use Disclaimer
  20
2 Server Board Overview

21
3 Functional Architecture

26
- Figure 3. Server Board SE7520JR2 Block Diagram
  26
- Processor Sub-System
  27
  - Processor Voltage Regulators
    27
  - Reset Configuration Logic
    27
  - Processor Module Presence Detection
    27
  - Gtl2006
    27
  - Common Enabling Kit (CEK) Design Support
    28
  - Processor Support
    28
    
    Figure 4. CEK Processor Mounting
    28
    
    Table 2: Processor Support Matrix
    28
    
    Jumperless Processor Speed Settings
    29
    
    Mixed Processor Cache Sizes
    29
    
    Mixed Processor Families
    29
    
    Mixed Processor Models
    29
    
    Mixed Processor Steppings
    29
    
    Processor Mis-Population Detection
    29
    
    EM64T Technology Support
    30
    
    Hyper-Threading Technology
    30
    
    Intel® Speedstep® Technology
    30
    
    Microcode
    30
    
    Processor Cache
    30
  - Multiple Processor Initialization
    30
  - CPU Thermal Sensors
    31
  - Processor Thermal Control Sensor
    31
  - Processor Thermal Trip Shutdown
    31
  - Processor IERR
    31
- Intel® E7520 Chipset
  31
  - Memory Controller Hub (MCH)
    32
    
    Front Side Bus (FSB)
    32
    
    MCH Memory Sub-System Overview
    32
    
    PCI Express
    32
    
    Hub Interface
    33
  - PCI-X Hub (PXH)
    33
    
    Full-Height Riser Slot
    33
    
    Low Profile Riser Slot
    33
    
    I/Oxapic Controller
    34
    
    Smbus Interface
    34
  - I/O Controller Hub (ICH5-R)
    34
    
    IDE Interface (Bus Master Capability and Synchronous DMA Mode)
    34
    
    PCI Interface
    34
    
    Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
    35
    
    Low Pin Count (LPC) Interface
    35
    
    SATA Controller
    35
    
    Enhanced Power Management
    36
    
    General Purpose I/O (GPIO)
    36
    
    Rtc
    36
    
    System Management Bus (Smbus 2.0)
    36
    
    Universal Serial Bus (USB) Controller
    36
- Memory Sub-System
  37
- I/O Sub-System
  47
  - PCI Subsystem
    47
    
    P32-A: 32-Bit, 33-Mhz PCI Subsystem
    48
    
    P64-A and P64-B: 64-Bit, 100Mhz PCI Subsystem
    48
    
    P64-Express: Dual X4 PCI Bus Segment
    48
    
    PCI Riser Slots
    48
    
    Table 7: PCI Bus Segment Characteristics
    48
    
    PCI Bus Numbering
    49
    
    PCI Scan Order
    49
    
    Device Number and IDSEL Mapping
    50
    
    Table 8: PCI Configuration Ids and Device Numbers
    51
    
    Automatic IRQ Assignment
    52
    
    Option ROM Support
    52
    
    PCI Apis
    52
    
    Resource Assignment
    52
  - Split Option ROM
    52
  - Interrupt Routing
    52
    
    Legacy Interrupt Routing
    52
    
    APIC Interrupt Routing
    53
    
    Table 9: PCI Interrupt Routing/Sharing
    53
    
    Legacy Interrupt Sources
    54
    
    Serialized IRQ Support
    54
    
    Table 10: Interrupt Definitions
    54
    
    Figure 8. Interrupt Routing Diagram (ICH5-R Internal)
    55
    
    IRQ Scan for PCIIRQ
    55
    
    Figure 9. Interrupt Routing Diagram
    56
    
    Figure 10. PCI Interrupt Mapping Diagram
    57
    
    Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card
    57
  - SCSI Support
    58
    
    LSI* 53C1030 Dual Channel Ultra320 SCSI Controller
    58
    
    Zero Channel RAID
    60
  - IDE Support
    60
    
    IDE Initialization
    61
    
    Ultra ATA/100
    61
  - SATA Support
    61
    
    Intel® RAID Technology Option ROM
    62
    
    Sata Raid
    62
  - Video Support
    62
    
    Video Modes
    62
    
    Table 11: Video Modes
    63
    
    Table 12: Video Memory Interface
    63
    
    Video Memory Interface
    63
    
    Dual Video
    64
  - Network Interface Controller (NIC)
    64
    
    NIC Connector and Status Leds
    65
  - USB 2.0 Support
    65
  - Super I/O Chip
    65
    
    Gpios
    65
    
    Table 13: Super I/O GPIO Usage Table
    65
    
    Serial Ports
    67
    
    Table 14: Serial a Header Pin-Out
    67
    
    Figure 12. Serial Port Mux Logic
    68
    
    Figure 13. RJ45 Serial B Port Jumper Block Location and Setting
    68
    
    Floppy Disk Support
    69
    
    Keyboard and Mouse Support
    69
    
    Removable Media Drives
    69
    
    Wake-Up Control
    69
  - BIOS Flash
    69
- Configuration and Initialization
  70
  - Memory Space
    70
    
    Figure 14. Intel ® Xeon™ Processor Memory Address Space
    70
    
    DOS Compatibility Region
    71
    
    Figure 15. DOS Compatibility Region
    71
    
    Extended Memory
    73
    
    Figure 16. Extended Memory Map
    73
    
    Memory Shadowing
    74
    
    System Management Mode Handling
    75
    
    Table 15: SMM Space Table
    75
  - I/O Map
    76
  - Table 16: I/O Map
    76
  - Accessing Configuration Space
    78
    
    CONFIG_ADDRESS Register
    79
- Clock Generation and Distribution
  79
4 System BIOS

80
5 Platform Management

113
- Table 45: Suppoted Management Features by Tier
  113
- Platform Management Architecture Overview
  115
  - Figure 19. On-Board Platform Management Architecture
    115
  - IPMI Messaging, Commands, and Abstractions XXX
    116
  - Standby
    116
  - IPMI 'Sensor Model
    117
  - Management Controllers
    118
  - Private Management Busses
    118
- On-Board Platform Management Features and Functionality
  121
- Mbmc Hardware Architecture
  123
  - Figure 21. External Interfaces to Mbmc
    123
  - Figure 22. Mbmc Block Diagram
    124
  - Power Supply Interface Signals
    124
  - Figure 23. Power Supply Control Signals
    125
  - Power Control Sources
    126
  - Power-Down Sequence
    126
  - Power-Up Sequence
    126
  - System Reset Control
    126
    
    Reset Signal Output
    126
    
    Table 47: Power Control Initiators
    126
    
    Control Panel System Reset
    127
    
    Reset Control Sources
    127
    
    Table 48: System Reset Sources and Actions
    127
    
    Control Panel Indicators
    128
    
    Power Led
    128
    
    Table 49: SSI Power LED Operation
    128
    
    Control Panel Inputs
    129
    
    Table 50: Fault / Status LED
    129
    
    Table 51: Chassis ID LED
    129
    
    Chassis Intrusion
    130
    
    Power Button
    130
    
    Reset Button
    130
  - Baseboard Fan Control
    131
  - Mbmc Peripheral Smbus
    131
  - Secure Mode Operation
    131
  - System Event Log (SEL)
    131
    
    SEL Erasure
    132
    
    Timestamp Clock
    132
  - Watchdog Timer
    131
  - Sensor Data Record (SDR) Repository
    132
    
    Initialization Agent
    132
  - Event Message Reception
    133
  - Field Replaceable Unit (FRU) Inventory Devices
    133
    
    Mbmc FRU Inventory Area Format
    133
  - NMI Generation
    133
  - SMI Generation
    133
  - Mbmc Self Test
    134
  - Messaging Interfaces
    134
    
    Channel Management
    134
    
    Host to Mbmc Communication Interface
    134
    
    Request/Response Protocol
    134
    
    Table 52: Suported Channel Assignments
    134
    
    User Model
    134
    
    LAN Interface
    135
    
    Table 53: LAN Channel Capacity
    135
  - Event Filtering and Alerting
    136
    
    Platform Event Filtering (PEF)
    136
    
    Alert over LAN
    137
  - Mbmc Sensor Support
    137
  - Table 54: PEF Action Priorities
    137
  - Table 55: Platform Sensors for On-Board Platform Instrumentation
    138
  - IMM BMC Sensor Support
    142
  - Table 56. Platform Sensors for Intel Management Modules - Professional and Advanced
    142
- System Management BIOS (SMBIOS)
  148
- Vital Product Data (VPD)
  148
- Wired for Management (WFM)
  148
6 Error Reporting and Handling

149
- Fault Resilient Booting (FRB)
  149
  - FRB1 - BSP Self-Test Failures
    149
  - FRB2 - BSP POST Failures
    149
  - FRB3 - BSP Reset Failures
    150
  - AP Failures
    151
  - Treatment of Failed Processors
    151
  - Memory Error Handling in RAS Mode
    152
  - Memory Error Handling in Non-RAS Mode
    153
  - Table 57: Memory Error Handling Mbmc Vs Sahalee
    153
  - DIMM Enabling
    154
  - Single-Bit ECC Error Throttling Prevention
    154
  - Table 58: Memory Error Handling in Non-RAS Mode
    154
- Error Logging
  155
  - PCI Bus Error
    155
  - Processor Bus Error
    155
  - Memory Bus Error
    156
  - System Limit Error
    156
  - Processor Failure
    156
  - Boot Event
    156
- Error Messages and Error Codes
  156
- Checkpoints
  167
- Light Guided Diagnostics
  174
7 Connectors and Jumper Blocks

175
8 Design and Environmental Specifications

202
- Server Board SE7520JR2 Design Specification
  202
- Power Supply Requirements
  202
  - Output Connectors
    202
  - Table 112: Board Design Specifications
    202
  - Figure 27. Power Harness Specification Drawing
    203
  - Table 113: P1 Main Power Connector
    204
  - Table 114: P2 Processor Power Connector
    204
  - Grounding
    205
  - Table 115: P3 Baseboard Signal Connector
    205
  - Table 116: Peripheral Power Connectors
    205
  - Table 117: P7 Hard Drive Power Connector
    205
  - Remote Sense
    206
  - Standby Outputs
    206
  - Voltage Regulation
    207
  - Dynamic Loading
    207
  - Table 118: Voltage Regulation Limits
    207
  - Table 119: Transient Load Requirements
    207
  - Capacitive Loading
    208
  - Closed Loop Stability
    208
  - Common Mode Noise
    208
  - Ripple / Noise
    208
  - Table 120: Capacitve Loading Conditions
    208
  - Table 121: Ripple and Noise
    208
  - Soft Starting
    209
  - Zero Load Stability Requirements
    209
  - Timing Requirements
    209
  - Table 122: Output Voltage Timing
    209
  - Figure 28. Output Voltage Timing
    210
  - Table 123: Turn On/Off Timing
    210
  - Residual Voltage Immunity in Standby Mode
    211
  - Figure 29. Turn On/Off Timing (Power Supply Signals)
    211
- Product Regulatory Compliance
  212
- Electromagnetic Compatibility Notices
  214
  - Fcc (Usa)
    214
  - Industry Canada (ICES-003)
    214
  - Europe (CE Declaration of Conformity)
    215
  - Taiwan Declaration of Conformity (BSMI)
    215
  - Korean Compliance (RRL)
    215
9 Miscellaneous Board Information

216
- Updating the System Software
  216
- Programming FRU and SDR Data
  216
- Clearing CMOS
  217
  - CMOS Clear Using J1H2 Jumper Block
    217
  - CMOS Clear Using Control Panel
    217
- BIOS Recovery Operation
  218
Appendix A: Integration and Usage Tips

221
- Glossary
  222
- Reference Documents
  225

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