System Bus Design Guidelines; System Bus Routing Guidelines; Initial Timing Analysis - Intel 815EG Design Manual

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System Bus Design Guidelines

The Pentium III processor delivers higher performance by integrating the Level 2 cache into the
processor and running it at the processor's core speed. The Pentium III processor runs at higher
core and system bus speeds than previous-generation IA-32 processors while maintaining
hardware and software compatibility with earlier Pentium III processors. The new Flip Chip-Pin
Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin
Grid Array (FC-PGA) packages using the PGA370 socket.
This section presents the considerations for designs capable of using the 815EG universal platform
with the full range of Pentium III processors using the PGA370 socket.
5.1

System Bus Routing Guidelines

The following layout guide supports designs using Pentium III processor (CPUID=068xh) /
Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors with the 815EG
chipset platform. The solution covers system bus speeds of 66/100/133 MHz for the Pentium III
processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket
370 processors. All processors must also be configured to 56 Ω on-die termination.
5.1.1

Initial Timing Analysis

Table 7 lists the AGTL/AGTL+ component timings of the processors and 815EG universal
platform's GMCH defined at the pins.
These timings are for reference only. Obtain each processor's specifications from the respective
processor datasheet and the chipset values from the appropriate 815 chipset datasheet.
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Intel 815EG Chipset Platform Design Guide
System Bus Design Guidelines
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