Configuration Address Register Mch Config_Address; Configuration Data Register Mch Config_Address; Configuration Registers; Addressing - Intel NetStructure MPCBL0001 Technical Product Specification

Addressing

5.1

Configuration Registers

5.1.1

Configuration Address Register MCH CONFIG_ADDRESS

I/O Address:
Default Value:
Access:
Size:
CONFIG_ADDRESS is a 32-bit I/O register that can be accessed only as a Dword. A byte or word
reference passes through the Configuration Address Register and hub link interface HI_A onto the
PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent PCI configuration access
is intended. This register is defined by the PCI Bus Specification.
Table 54.

Configuration Address Register Bit Assignments

Bit
0
Bit
31
30:24
23:16
15:11
10:8
7:2
1:0
5.1.2

Configuration Data Register MCH CONFIG_ADDRESS

I/O Address:
Default Value:
Access:
Size:
Technical Product Specification
Order #273817
®
Intel NetStructure MPCBL0001 High Performance Single Board Computer
0x0CF8 Accessed as a Dword
0x00000000
Read/Write
32 bits
31 30 24 23
R 0
Configuration Enable (CFGE): When this bit is set to 1, accesses to the PCI configuration space
are enabled. When this bit is reset to 0, accesses to the PCI configuration space are disabled.
Reserved (These bits are read only and have a value of 0).
Bus Number: Contains the bus number being targeted by the configuration cycle.
Device Number: Selects one of the 32 possible devices per bus.
Function Number: Selects one of eight possible functions within a device.
Register Number: This field selects one register within a particular bus, device, and function as
specified by the other fields in the Configuration Address Register. This field is mapped to A[7:2]
during HI_A-D configuration cycles.
Reserved.
0x0CFC
0x0000000
Read/Write
32 bits
16 15 11 10
0 0
Description
Contents
5
8 7 2 1 0
0 R Default
95