Avaya S8700 Maintenance Manual page 2252

Maintenance-Object Repair Procedures
6. For unduplicated Tone-Clock circuit packs in a slave port network:
8-1530 Issue 1 May 2002
Replace the active Expansion Interface circuit pack in the
master port network.
In a CSS configuration, replace the Switch Node Interface
circuit pack connected to the active Expansion Interface
circuit pack in the master port network. The list fiber-link
command can be used to determine the Switch Node
Interface circuit pack that is connected to the active
Expansion Interface circuit pack in the master port network.
If the system's synchronization reference is a Tone-Clock
circuit pack or a Stratum-3 clock, follow normal escalation
procedures.
If the system's primary synchronization reference is a DS1
Interface circuit pack, assign a different DS1 Interface as the
primary reference. If the problem persists and any slip errors
remain, follow the procedures described in the
troubleshooting section above.
Enter set tone-clock UUC command to switch the
Tone-Clock in the master port network.
If the problem still persists, enter set tone-clock UUC to
switch the Tone-Clocks in the master port network back to
their previous configuration.
Enter the test Tone-Clock UUC long command to test the
Tone-Clock in the master and slave port networks.
Check the Error Log for TDM-CLK errors and verify that TDM
Bus Clock Circuit Status Inquiry test (#148) passes.
If Test #148 fails with an Error Code 2–32, see
(TDM Bus Clock)'' to resolve the problem. If not, continue
with the following steps.
If the master and slave Tone-Clock circuit packs do not fail
TDM Bus Clock Test #150 (TDM Bus Clock PPM Inquiry
test), replace the Expansion Interface circuit packs that have
EXP-INTF error 2305.
If the system synchronization reference is a Tone-Clock
circuit pack and the master Tone-Clock circuit pack fails TDM
Bus Clock Test #150, follow the steps listed in "TDM-CLK" to
replace the master Tone-Clock circuit pack.
If the system's synchronization reference is a DS1 Interface
circuit pack and the master Tone-Clock circuit pack fails TDM
Bus Clock test (#150), the primary or secondary (if
administered) synchronization references are not providing
valid timing signals for the system.
''TDM-CLK
555-233-143