Transmit Interrupt Status (Unmasked) Register (Txintstatraw); Transmit Interrupt Status (Unmasked) Register (Txintstatraw) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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5.7

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)

The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in
described in Table
Figure 47. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
31
15
7 6
TX7PEND TX6PEND
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 46. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 TX7PEND 0-1
6 TX6PEND 0-1
5 TX5PEND 0-1
4 TX4PEND 0-1
3 TX3PEND 0-1
2 TX2PEND 0-1
1 TX1PEND 0-1
0 TX0PEND 0-1
SPRUEQ6 – December 2007
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46.
5 4
TX5PEND TX4PEND
R-0 R-0
Description
Reserved
TX7PEND raw interrupt read (before mask)
TX6PEND raw interrupt read (before mask)
TX5PEND raw interrupt read (before mask)
TX4PEND raw interrupt read (before mask)
TX3PEND raw interrupt read (before mask)
TX2PEND raw interrupt read (before mask)
TX1PEND raw interrupt read (before mask)
TX0PEND raw interrupt read (before mask)
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Reserved
R-0
Reserved
R-0
3 2
TX3PEND TX2PEND
R-0 R-0
Figure 47 and
16
8
1 0
TX1PEND TX0PEND
R-0 R-0
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