Table of Contents
Advertisement
(3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1)
These registers set the serial clock for UARTn.
BRGCn can be set by an 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 10-31 shows the format of BRGCn.
Figure 10-31. Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
After reset: 00H
7
BRGCn
MDLn7
(n = 0, 1)
MD
MD
Ln
Ln6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
1
1
Cautions 1. Before starting operation, select a setting other than "Setting prohibited". Selecting the
"Setting prohibited" setting in stop mode does not cause any problems.
2. If write is performed to BRGCn during communication processing, the output of the baud
rate generator will be disturbed and communication will not be performed normally.
Therefore, do not write to BRGCn during communication processing.
Remark
f
: Source clock of 8-bit counter
SCK
(4) Baud rate generator mode control registers 0, 1 (BRGMC0, BRGMC1)
These registers set the UARTn source clock.
BRGMCn is set by an 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 10-32 shows the format of BRGMCn.
CHAPTER 10
SERIAL INTERFACE FUNCTION
R/W
Address: FFFFF304H, FFFFF314H
6
5
MDLn6
MDLn5
MD
MD
MD
MD
MD
Ln5
Ln4
Ln3
Ln2
Ln1
×
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
4
3
MDLn4
MDLn3
MDLn2
MD
Selection of Input Clock
Ln
0
×
×
Setting prohibited
0
0
f
/8
SCK
0
1
f
/9
SCK
1
0
f
/10
SCK
1
1
f
/11
SCK
0
0
f
/12
SCK
0
1
f
/13
SCK
1
0
f
/14
SCK
1
1
f
/15
SCK
0
0
f
/16
SCK
•
•
•
•
•
•
1
1
f
/255
SCK
2
1
0
MDLn1
MDLn0
•
•
•
k
−
8
9
10
11
12
13
14
15
16
•
•
•
255
285
Advertisement
Table of Contents
