Noise Elimination; Interrupt Trigger Mode Selection - NEC V850E/MA1 User Manual

CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION

7.3.8 Noise elimination

The noise of the INTPn, INTPm, and TI000 to TI030 pins is eliminated with analog delay (n = 000, 001, 010, 011,
020, 021, 030, 031, m = 103 to 100, 113 to 110, 123 to 120, and 133 to 130). The delay time is about 60 to 220 ns.
A signal input that changes within the delay time is not internally acknowledged.

7.3.9 Interrupt trigger mode selection

The valid edge of pins INTP0n0, INTP0n1, INTP1nm, ADTRG, and TI0n0 can be selected by program. Moreover,
a level trigger can be selected for the INTP1nm pin (n = 0 to 3, m = 0 to 3). The edge that can be selected as the
valid edge is one of the following.
• Rising edge
• Falling edge
• Both the rising and falling edges
When the INTP0n0, INTP0n1, INTP1nm, ADTRG, and TI0n0 pins are edge-detected, they become interrupt
sources and capture trigger, A/D trigger, and timer external count inputs (n = 0 to 3, m = 0 to 3).
The valid edge is specified by external interrupt mode registers 1 to 4 (INTM1 to INTM4) and valid edge select
registers (SESC0 to SESC3). The level trigger is specified by external interrupt mode registers 1 to 4 (INTM1 to
INTM4).
(1) External interrupt mode registers 1 to 4 (INTM1 to INTM4)
These registers specify the trigger mode for external interrupt requests (INTP100 to INTP103, INTP110 to
INTP113, INTP120 to INTP122, INTP123/ADTRG, INTP130 to INTP133), input via external pins.
correspondence between each register and the external interrupt requests that register controls is shown
below.
• INTM1: INTP100 to INTP103
• INTM2: INTP110 to INTP113
• INTM3: INTP120 to INTP122, INTP123/ADTRG
• INTM4: INTP130 to INTP133
INTP123 is the alternate function pin of the A/D converter external trigger input (ADTRG). Therefore, when
INTP123/ADTRG is set to the external trigger mode by the TRG0 to TRG2 bits of the A/D converter mode
register (ADM), the ES1231 and ES1230 bits specify the valid edge of the external trigger input (ADTRG).
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and
falling edges).
These registers can be read/written in 8-bit units.
Caution Before setting the INTP1nm or ADTRG pin in the trigger mode, set the PMCn register.
If the PMCx register is set after the INTM1 to INTM4 registers have been set, an illegal
interrupt may occur depending on the timing of setting the PMCn register (n = 0 to 3, m = 0
to 3, x = 0, 2, or 3).
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