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11.3 Clock Output Control Controller Registers
The following two types of registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 6 (PM6)
(1) Clock output selection register (CKS)
This register sets output clock.
CKS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CKS to 00H.
Caution To enable PCL output, set CCS0 to CCS2, and then set CLOE to 1 by using a 1-bit memory
manipulation instruction.
Figure 11-2. Clock Output Selection Register (CKS) Format
Address: FF40H After Reset: 00H R/W
Symbol
7
CKS
0
CLOE
0
1
CCS2
0
0
0
0
1
1
1
1
Cautions 1. When rewriting CKS to other data, stop the timer operation beforehand.
2. Bits 3 and 5 to 7 must be set to 0.
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses apply to operation with f
150
CHAPTER 11 CLOCK OUTPUT CONTROLLER
6
5
0
0
CLOE
PCL Output Enable/Disable Specification
Operation disabled.
Operation enabled.
CCS1
CCS0
0
0
f
(8.38 MHz)
X
0
1
f
/2 (4.19 MHz)
X
2
1
0
f
/2
X
3
1
1
f
/2
X
4
0
0
f
/2
X
5
0
1
f
/2
X
6
1
0
f
/2
X
7
1
1
f
/2
X
Preliminary User's Manual U14581EJ3V0UM00
4
3
2
0
CCS2
PCL Output Clock Selection
(2.09 MHz)
(1.04 MHz)
(524 kHz)
(262 kHz)
(131 kHz)
(65.5 kHz)
= 8.38 MHz.
X
1
0
CCS1
CCS0
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