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16.3 LCD Controller/Driver Control Registers
The LCD controller/driver is controlled by the following two registers.
• LCD display mode register (LCDM)
• LCD display control register (LCDC)
(1) LCD display mode register (LCDM)
This register sets display operation enabling/disabling, the LCD clock, frame frequency.
LCDM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM to 00H.
Figure 16-3. LCD Display Mode Register (LCDM) Format
Address: FFB0H
After Reset: 00H
Symbol
7
LCDM
LCDON
LCDON
0
1
LCDM6
0
0
0
0
Other than above
Remark f
= Main system clock oscillation frequency
X
192
CHAPTER 16 LCD CONTROLLER/DRIVER
R/W
6
5
LCDM6
LCDM5
LCDM4
LCD Display Enable/Disable
Display off (all segment outputs are non-select signal outputs)
Display on
LCDM5
LCDM4
17
0
0
f
/2
X
16
0
1
f
/2
X
15
1
0
f
/2
X
14
1
1
f
/2
X
Setting prohibited
4
3
2
0
0
LCD Clock Selection (f
(64 Hz)
(128 Hz)
(256 Hz)
(512 Hz)
1
0
0
0
= 8.38 MHz)
X
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