Features - NEC mPD784225 Series User Manual

1.1 Features

• Inherits the peripheral functions of the µ PD780058 Subseries
•
Minimum instruction execution time
• 160 ns (main system clock: @ f
• 61 µ s (subsystem clock: @ f
•
Instruction set suited to control applications
•
Interrupt controller (4-level priority)
• Vectored interrupt servicing, macro service, context switching
•
Standby function
• HALT, STOP, IDLE modes
• In the low power consumption mode: HALT, IDLE modes (subsystem clock operation)
•
On-chip memory: Mask ROM
Flash memory 128 KB ( µ PD78F4225)
RAM
•
I/O pins: 67
• Software-programmable pull-up resistors: 57 inputs
• LED direct drive possible: 16 outputs
• Timers: 16-bit timer/event counter × 1 unit
8-bit timer/event counter × 2 units
8-bit timer × 2 units
•
Watch timer: 1 channel
•
Watchdog timer: 1 channel
•
Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
Note
• CSI/IIC0 (3-wire serial I/O, multimaster supporting I
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
•
Real-time output port (by combining with the timer/counters, two stepper motors can be independently controlled.)
•
Clock frequency division function
•
Clock output function: Select from f
•
Buzzer output function: Select from f
•
Power supply voltage: V
Note Only in the µ PD784225Y Subseries
CHAPTER 1 OVERVIEW
= 12.5 MHz operation)
XX
= 32.768 kHz operation)
XT
128 KB ( µ PD784225)
96 KB ( µ PD784224)
4,352 bytes ( µ PD784225, 78F4225)
3,584 bytes ( µ PD784224)
2
, f /2, f /2
XX XX XX
10 11
/2 , f /2
XX XX
= 1.8 to 5.5 V ( µ PD784224, 784225, 784224Y, 784225Y)
DD
= 1.9 to 5.5 V ( µ PD78F4225, 78F4225Y only)
V
DD
User's Manual U12697EJ3V0UM
2 Note
C bus ): 1 channel
3 4 5
, f /2 , f /2 , f /2 , f /2
XX XX XX XX
12 13
, f /2 , f /2
XX XX
6 7
, f /2 , f
XX XT
33