Features - NEC V850E/MA1 User Manual

1.2 Features

Number of instructions:
Minimum instruction execution time:
General-purpose registers:
Instruction set:
Memory space:
External bus interface:
Internal memory
Interrupts/exceptions:
Memory access controller
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CHAPTER 1 INTRODUCTION
83
20 ns (at internal 50 MHz operation)
32 bits × 32
V850E1 CPU
Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits →
64 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection
function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
256 MB linear address space (common program/data use)
Chip select output function: 8 spaces
Memory block division function: 2, 4, 8 MB/block
Programmable wait function
Idle state insertion function
16-bit data bus (address/data separated)
16-/8-bit bus sizing function
Bus hold function
External wait function
Address setup wait function
Endian control function
Part Number
µ PD703103A
None
µ PD703105A
128 KB (Mask ROM)
µ PD703106A
128 KB (Mask ROM)
µ PD703107A
256 KB (Mask ROM)
µ PD70F3107A
256 KB (Flash memory)
External interrupts: 25 (including NMI)
Internal interrupts: 33 sources
Exceptions: 1 source
Eight levels of priorities can be set.
DRAM controller (compatible with EDO DRAM and SDRAM)
Page ROM controller
User's Manual U14359EJ4V0UM
Internal ROM
4 KB
4 KB
10 KB
10 KB
10 KB
Internal RAM