System Register Set - NEC V850/SB1 User Manual

3.2.2 System register set

System registers control the status of the CPU and hold interrupt information.
No. System Register Name
0 EIPC
1 EIPSW
2 FEPC
3 FEPSW
4 ECR
5 PSW
6 to 31 Reserved
To read/write these system registers, specify a system register number indicated by the system register load/store
instruction (LDSR or STSR instruction).
(1) Interrupt source register (ECR)
After reset: 00000000H
Symbol 31
ECR
FECC Exception code of NMI (For exception code, refer to Table 5-1.)
EICC Exception code of exception/interrupt
CHAPTER 3
Table 3-2. System Register Numbers
Usage
Interrupt status saving registers
NMI status saving registers
Interrupt source register
Program status word
16
FECC
User's Manual U13850EJ6V0UD
CPU FUNCTIONS
These registers save the PC and PSW when an
exception or interrupt occurs. Because only one set of
these registers is available, their contents must be
saved when multiple interrupts are enabled.
These registers save PC and PSW when NMI occurs.
If exception, maskable interrupt, or NMI occurs, this
register will contain information referencing the
interrupt source. The higher 16 bits of this register are
called FECC, to which exception code of NMI is set.
The lower 16 bits are called EICC, to which exception
code of exception/interrupt is set.
A program status word is a collection of flags that
indicate program status (instruction execution result)
and CPU status.
15
EICC
Operation
0
99