System Register Set - NEC V850E/MS1 UPD703100 User Manual

3.2.2 System register set

System registers control the status of the CPU and hold interrupt information.
No. System Register Name
0 EIPC
1 EIPSW
2 FEPC
3 FEPSW
4 ECR
5 PSW
16 CTPC
17 CTPSW
18 DBPC
19 DBPSW
20 CTBP
6 to 15 Reserved
21 to 31
To read/write these system registers, specify the system register number indicated by a system register load/store
instruction (LDSR or STSR instruction).
31
ECR
Bit Position Bit Name
31 to 16 FECC
15 to 0 EICC
72
CHAPTER 3 CPU FUNCTION
Table 3-2. System Register Numbers
Usage
Status saving register during
interrupt
Status saving register during
NMI
Interrupt source register
Program status word
Status saving register during
CALLT execution
Status saving register during
exception trap
CALLT base pointer
Figure 3-2. Interrupt Source Register (ECR)
16 15
FECC
Fatal Error Cause Code
Exception code of NMI (refer to Table 7-1 Interrupt List)
Exception/Interrupt Cause Code
Exception code of exception/interrupt (refer to Table 7-1 Interrupt List)
User's Manual U12688EJ4V0UM00
Operation
These registers save the PC and PSW when a
software exception or interrupt occurs. Because only
one set of these registers is available, their contents
must be saved when multiple interrupts are enabled.
These registers save the PC and PSW when an NMI
occurs.
If an exception, maskable interrupt, or NMI occurs,
this register will contain information referencing the
interrupt source. The higher 16 bits of this register
are called FECC, to which the exception code of the
NMI is set. The lower 16 bits are called EICC, to
which the exception code of the exception/interrupt is
set.
Refer to Figure 3-2.
The program status word is a collection of flags that
indicate the program status (instruction execution
result) and CPU status.
Refer to Figure 3-3.
If the CALLT instruction is executed, this register
saves the PC and PSW.
If an exception trap is generated due to detection of
an illegal instruction code, this register saves the PC
and PSW.
This is used to specify the table address and
generate the target address.
0
EICC
Function
After reset
00000000H