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3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, use the system register load/store instruction (LDSR or STSR
instruction) with a specific system register number indicated below.
No.
0
Status saving register during interrupt (EIPC)
1
Status saving register during interrupt (EIPSW)
2
Status saving register during NMI (FEPC)
3
Status saving register during NMI (FEPSW)
4
Interrupt source register (ECR)
5
Program status word (PSW)
Reserved number for future function expansion (operations that
6 to 15
access these register numbers cannot be guaranteed).
16
Status saving register during CALLT execution (CTPC)
17
Status saving register during CALLT execution (CTPSW)
18
Status saving register during exception/debug trap (DBPC)
19
Status saving register during exception/debug trap (DBPSW)
20
CALLT base pointer (CTBP)
Reserved number for future function expansion (operations that
21 to 31
access these register numbers cannot be guaranteed).
Notes: 1. Because this register has only one set, to approve multiple interrupts, it is necessary to save
this register by program.
2. Access is only possible while the DBTRAP instruction is executed.
Caution:
Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 with the LDSR instruction, bit 0 will be
ignored when the program returned by RETI instruction after interrupt servicing
(because bit 0 of the PC is fixed to 0). When setting the value of EIPC, FEPC, or CTPC,
use the even value (bit 0 = 0).
Remark:
O: Access allowed
×:
Access prohibited
58
Chapter 3 CPU Function
Table 3-2: System Register Numbers
System Register Name
Preliminary User's Manual U15839EE1V0UM00
LDSR Instruction
Note 1
Operand Specification
STSR Instruction
O
O
O
O
O
O
O
O
×
O
O
O
×
×
O
O
O
O
Note 2
O
O
Note 2
O
O
O
O
×
×
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