Mitsubishi Electric MELSEC iQ-R Series User Manual page 507

Class3/UCMM tag communication area
■Class3/UCMM data area (tag communications) (Un\G8278016 to Un\G8462847)
The data sent to and received from the EtherNet/IP device is stored during Class3/UCMM tag communications.
The storage area is reserved in the order of connection No.1 to 256 from the top of this area.
■Class3/UCMM data size (tag communications) (Un\G8463104 to Un\G8463359)
The size of the data (unit: words) sent to and received from the EtherNet/IP device during Class3/UCMM tag communications
is stored in the order of connection No.1 to 256.
■Class3/UCMM start offset address to the data (tag communications) (Un\G8463616 to
Un\G8464127)
The offset address of "Class3/UCMM data area (tag communications)" (Un\G8278016 to Un\G8462847), where the data to be
sent to and received from the EtherNet/IP device during Class3/UCMM tag communications is stored, is stored in double-
word units in the order of connection No.1 to 256.
• 0 to 184831 (0H to 2D1FFH): The address is stored as an offset address.
• 4294967295 (FFFFFFFFH): No address is assigned as an offset address.
Class3/UCMM communication status
■Class3 reserved station (Un\G8464416 to Un\G8464431)
Stores the setting status of the reserved station of connection numbers 1 to 256.
• On: Reserved station
• Off: Not set as reserved station
The following table lists the assignments for each area.
The value of each bit indicates the connection number.
Address
Class3 reserved station
Un\G8464416
Un\G8464417
Un\G8464418
Un\G8464419
Un\G8464420
Un\G8464421
Un\G8464422
Un\G8464423
Un\G8464424
Un\G8464425
Un\G8464426
Un\G8464427
Un\G8464428
Un\G8464429
Un\G8464430
Un\G8464431
Bit
b15 b14 b13 b12 b11 b10 b9
16 15 14 13 12 11
32 31 30 29 28 27
48 47 46 45 44 43
64 63 62 61 60 59
80 79 78 77 76 75
96 95 94 93 92 91
112 111 110 109 108 107
128 127 126 125 124 123
144 143 142 141 140 139
160 159 158 157 156 155
176 175 174 173 172 171
192 191 190 189 188 187
208 207 206 205 204 203
224 223 222 221 220 219
240 239 238 237 236 235
256 255 254 253 252 251
b8 b7 b6 b5 b4
10 9 8 7 6 5
26 25 24 23 22 21
42 41 40 39 38 37
58 57 56 55 54 53
74 73 72 71 70 69
90 89 88 87 86 85
106 105 104 103 102 101
122 121 120 119 118 117
138 137 136 135 134 133
154 153 152 151 150 149
170 169 168 167 166 165
186 185 184 183 182 181
202 201 200 199 198 197
218 217 216 215 214 213
234 233 232 231 230 229
250 249 248 247 246 245
Appendix 3 Buffer Memory
b3 b2 b1 b0
A
4 3 2 1
20 19 18 17
36 35 34 33
52 51 50 49
68 67 66 65
84 83 82 81
100 99 98 97
116 115 114 113
132 131 130 129
148 147 146 145
164 163 162 161
180 179 178 177
196 195 194 193
212 211 210 209
228 227 226 225
244 243 242 241
APPX
505