Mitsubishi Electric MELSEC iQ-R Series User Manual page 161

■Data assurance at the time of access to buffer memory
The 32-bit data can be assured by satisfying the following conditions:
• Access using the DMOV instruction
• The start address of the buffer memory is a multiple of 2.
U0 \
DMOV K100 G10
Station-based block data assurance
Cyclic data is assured for each station by handshake between the CPU module and the CC-Link IE TSN Plus module for a
link refresh. The link device is assured as follows.
• RX, RY, RWw, and RWr data are assured for each station
• LB and LW data are assured for each station
■Setting
Set station-based block data assurance under "Supplementary Cyclic Settings" in "Application Settings" of the master station.
( Page 86 Supplementary Cyclic Settings)
Once this setting is enabled on the master station, the data for all stations is assured for each station.
■Access to link devices
During a link refresh, data is assured for each station as shown below.
CPU module
Device
Data Station
assurance No.1
Data Station
assurance No.2
Data Station
assurance No.3
Data Station
assurance No.4
■Precautions
RX, RY, RWw, and RWr data cannot be assured for each station with LB and LW data.
DMOV instruction
CC-Link IE TSN Plus module
Link device
Station
No.1
Station
No.2
Link refresh
Station
No.3
Station
No.4
CC-Link IE TSN Plus module
Buffer memory
2 words 0H
(32 bits)
1H
2H
2 words
(32 bits)
3H
4H
2 words
(32 bits)
5H
6H
2 words
(32 bits)
7H
Data
assurance
Data
assurance
Data
assurance
Data
assurance
9 FUNCTIONS
159
9.2 Cyclic Transmission
9