Mitsubishi Electric MELSEC iQ-R Series User Manual page 497

Class1 cyclic pause
■Class1 cyclic pause specification (Un\G7735808 to Un\G7735823)
This area specifies the connection to request cyclic pause among Class1 communication connections No.1 to No.256.
• 0: Cyclic pause not requested
• 1: Cyclic pause requested
The following table lists the assignments for each area.
The value of each bit indicates the connection number.
Address Bit
b15 b14
Un\G7735808 16 15
Un\G7735809 32 31
Un\G7735810 48 47
Un\G7735811 64 63
Un\G7735812 80 79
Un\G7735813 96 95
Un\G7735814 112 111
Un\G7735815 128 127
Un\G7735816 144 143
Un\G7735817 160 159
Un\G7735818 176 175
Un\G7735819 192 191
Un\G7735820 208 207
Un\G7735821 224 223
Un\G7735822 240 239
Un\G7735823 256 255
■Class1 cyclic pause status (Un\G7735824 to Un\G7735839)
This area stores the results of the cyclic pause request among Class1 communication connections No.1 to No.256.
• 0: Cyclic executing
• 1: Cyclic paused
The following table lists the assignments for each area.
The value of each bit indicates the connection number.
Address Bit
b15 b14
Un\G7735824 16 15
Un\G7735825 32 31
Un\G7735826 48 47
Un\G7735827 64 63
Un\G7735828 80 79
Un\G7735829 96 95
Un\G7735830 112 111
Un\G7735831 128 127
Un\G7735832 144 143
Un\G7735833 160 159
Un\G7735834 176 175
Un\G7735835 192 191
Un\G7735836 208 207
Un\G7735837 224 223
Un\G7735838 240 239
Un\G7735839 256 255
b13 b12 b11 b10 b9
14 13 12 11 10
30 29 28 27 26
46 45 44 43 42
62 61 60 59 58
78 77 76 75 74
94 93 92 91 90
110 109 108 107 106
126 125 124 123 122
142 141 140 139 138
158 157 156 155 154
174 173 172 171 170
190 189 188 187 186
206 205 204 203 202
222 221 220 219 218
238 237 236 235 234
254 253 252 251 250
b13 b12 b11 b10 b9
14 13 12 11 10
30 29 28 27 26
46 45 44 43 42
62 61 60 59 58
78 77 76 75 74
94 93 92 91 90
110 109 108 107 106
126 125 124 123 122
142 141 140 139 138
158 157 156 155 154
174 173 172 171 170
190 189 188 187 186
206 205 204 203 202
222 221 220 219 218
238 237 236 235 234
254 253 252 251 250
b8 b7 b6 b5 b4
9 8 7 6 5
25 24 23 22 21
41 40 39 38 37
57 56 55 54 53
73 72 71 70 69
89 88 87 86 85
105 104 103 102 101
121 120 119 118 117
137 136 135 134 133
153 152 151 150 149
169 168 167 166 165
185 184 183 182 181
201 200 199 198 197
217 216 215 214 213
233 232 231 230 229
249 248 247 246 245
b8 b7 b6 b5 b4
9 8 7 6 5
25 24 23 22 21
41 40 39 38 37
57 56 55 54 53
73 72 71 70 69
89 88 87 86 85
105 104 103 102 101
121 120 119 118 117
137 136 135 134 133
153 152 151 150 149
169 168 167 166 165
185 184 183 182 181
201 200 199 198 197
217 216 215 214 213
233 232 231 230 229
249 248 247 246 245
b3 b2 b1 b0
4 3 2 1
20 19 18 17
36 35 34 33
52 51 50 49
68 67 66 65
84 83 82 81
100 99 98 97
116 115 114 113
132 131 130 129
148 147 146 145
164 163 162 161
180 179 178 177
196 195 194 193
212 211 210 209
228 227 226 225
244 243 242 241
b3 b2 b1 b0
4 3 2 1
20 19 18 17
36 35 34 33
52 51 50 49
68 67 66 65
84 83 82 81
100 99 98 97
116 115 114 113
132 131 130 129
148 147 146 145
164 163 162 161
180 179 178 177
196 195 194 193
212 211 210 209
228 227 226 225
244 243 242 241
APPX
Appendix 3 Buffer Memory
A
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