Renesas M16C Series User Manual page 115

M30240 Group
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
2
RxD
2
Signal conductor level
(Note 2)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Transfer clock
Receive enable
bit (RE)
RxD
2
TxD
2
Signal conductor level
(Note 2)
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.92: Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Rev.1.00 Sep 24, 2003 Page 97 of 360
Tc
"1"
"0"
Data is set in UART2 transmit buffer register
"1"
"0"
Start
bit
ST D D
D D D
0 1 2 3 4
ST
D D D D D
0 1 2 3 4
"1"
"0"
"1"
"0"
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = "1".
Tc
"1"
"0"
Start
bit
ST D D D D D
0 1 2 3 4
ST D D D D D
0 1 2 3 4
"1"
"0"
"1"
"0"
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = "0".
Note 1
Transferred from UART2 transmit buffer register to UART2 transmit register
Parity Stop
bit bit
D ST D
D D P SP
5 7 0
6
A "L" level returns from TxD
the occurrence of a parity error.
D
D D P SP
7 ST D
5 6
0
The level is detected by the
interrupt routine.
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
Parity
Stop
bit
bit
D D D P SP ST D
5 6 7 0
A "L" level returns from TxD
the occurrence of a parity error.
D D D P SP ST D
5 6 7 0
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
UART0 to UART2
D D D D D D D P
1 2 3 4 5 6 7
SP
due to
2
SP
D D D D D D D P
1 2 3 4 5 6 7
, f , f )
1 8 32
SP
D D D D D D D P
1 2 3 4 5 6 7
due to
2
SP
D D D D D D D P
1 2 3 4 5 6 7
Read to receive buffer
, f , f )
1 8 32
The level is
detected by the
interrupt routine.