Renesas M16C Series User Manual page 323

M30240 Group
• UNDER_RUN Flag
This bit is used for isochronous transfers only.The USB FCU sets this bit to "1" when a FIFO underrun
is detected. When interrupts are enabled, a USB overrun/underrun interrupt occurs. Write a "0" to clear
this bit.
• SEND_STALL Bit
When a STALL condition exists, this bit should be set to"1". When this bit is "1", the USB function con-
trol unit sends a STALL handshake signal to the host CPU. Write a "0" to clear this bit.
• ISO/TOGGLE_INIT Bit
The ISO/TOGGLE_INIT bit performs the double function of an ISO bit and a TOGGLE_INIT bit.
• ISO bit:
This bit should be set to "1" when an endpoint is used for isochronous transfer. When the ISO bit is set to "1",
the device uses DATA0 as the PID for all packets sent to the host. This bit should be fixed at "1" while an
isochronous transfer is taking place.
• TOGGLE_INIT bit:
By setting the TOGGLE_INIT bit to "1" the PID of all packets transmitted to the host is set to DATA0. To ini-
tialize the toggle sequence of the endpoint (reset the data packet to DATA0), this bit should be set to "1" and
after that data packet, it should be cleared to "0".
• INTPT Bit
This bit should be set to"1" when the IN endpoint is used to communicate rate feedback information.
When the INTPT bit is set, each time a data packet is transmitted to the host, regardless of when there
is a handshake packet or the type of packet, the data toggle is switched.
• TX_NOT_EPT Flag
This becomes"1" when there is at least one data packet within the IN FIFO.
• FLUSH Bit
This bit should be set to "1" to flush data within the IN FIFO. When there is one packet in the FIFO, a
flush causes the FIFO to empty. When there are two packets in the FIFO, a flush causes the older
packet to be flushed out of the FIFO.
• AUTO_SET Bit
When this bit is set to "1", the IN_PKT_RDY bit is set automatically by the USB Function Control unit
when a data packet equal to the MaxP is written into the IN FIFO. However, when a short packet (data
packet that is less than the maximum packet size) is transmitted, the IN_PKT_RDY should be set to"1"
by the CPU after the data has been written to the IN FIFO.
Figure 3.20 shows the structure of the USB Endpoint x IN Control/Status Register.
Rev.1.00 Sep 24, 2003 Page 305 of 360
Universal Serial Bus