Renesas M16C Series User Manual page 79

M30240 Group
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
Note: Pointer is incremented by
Figure 1.53: Block diagram of DMAC
DMAi request cause select register
b7 b6 b5 b4 b3 b2
Figure 1.54: DMAC register (1)
Rev.1.00 Sep 24, 2003 Page 61 of 360
(addresses 0029 , 0028
16
(addresses 0039 , 0038
16
Data bus low-order bits
Data bus high-order bits
a DMA request.
Symbol
b1 b0
DMiSL (i=0,1) 03B8
Bit name
Bit symbol
DSEL0
DMA request cause
DSEL1 select bits
DSEL2
DSEL3
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Software DMA
DSR
request bit
Note 1: Address 03B8 is for INT0, 3BA
16
Note 2: Address 03B8 is for UART1 transmit, 03BA
16
Note 3: Address 03B8 is for USB0, 03BA
16
Address bus
DMA0 source pointer SAR0(20)
(addresses 0022
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20)
DMA1 source pointer SAR1 (20)
) (addresses 0032
16
DMA1 destination pointer DAR1 (20)
a
DMA1 forward address pointer (20)
)
16
DMA latch high-order bits
Address
, 03BA
16 16
Function (Note)
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 /INT1pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
USB0/USB1 (Note 3)
1 0 0 1 :
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit/UART receive (Note 2)
If software trigger is selected, a DMA request is generated by
setting this bit to "1" (When read, the value of this bit is always "0")
is for INT1.
16
is for UART1 receive.
16
is for USB1.
16
to 0020 )
16 16
(addresses 0026 to 0024 )
16 16
(Note)
to 0030 )
16 16
(addresses 0036 to 0034 )
16 16
(Note)
DMA latch low-order bits
When reset
00
16
R W
DMAC