Renesas M16C Series User Manual page 75

M30240 Group
The CPU writes a "1" to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes
the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be
flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredict-
able results.
• INxCSR7 (AUTO_SET):
When the CPU sets this bit to a "1", the IN_PKT_RDY bit is set automatically by the USB FCU after the number
of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see "IN (Transmit)
FIFO" operation for details).
USB Endpoint x IN Control and Status Register (Note 5)
b7 b6 b5 b4 b3 b2
Figure 1.47: USB Endpoint x IN CSR
1.2.18.4.15 USB Endpoint x OUT Control and Status Register
The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.48 contains control and sta-
tus information of the respective OUT Endpoint 1-4.
• OUTxCSR0 (OUT_PKT_RDY):
The OUTxCSR0 bit for the OUT FIFO status (see "OUT (Receive) FIFOs" for details).
The USB FCU sets this bit to a "1" and updates the FIFO pointers after a data packet has been successfully
received from the host. The CPU writes a "0" to this bit to inform the USB FCU that a data packet has been
unloaded. The USB FCU updates the FIFO pointers when this occurs. The CPU must allow at least one clock
cycle between writing and reading bit OUTxCSR0.
• OUTXxCSR1 (OVER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this
bit to a "1" at the beginning of an OUT token when two data packets are already present in the FIFO. Setting
this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear
OUTXCSR1.
• OUTxCSR2 (SEND_STALL):
The CPU writes a "1" to this bit when the endpoint is stalled. The USB FCU returns a STALL handshake while
this bit is set. The CPU writes a "0" to clear this bit.
• OUTxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration
of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a "1", the device accepts either DATA0 or
DATA1 for the PID sent by the host.
Rev.1.00 Sep 24, 2003 Page 57 of 360
b1 b0
Symbol
EPiICS (i= 1-4)
Bit symbol Bit name
IN_PKT_RDY Bit
INxCSR0
UNDER_RUN Flag
INxCSR1
SEND_STALL Bit
INxCSR2
ISO Bit
INxCSR3
INTPT
INxCSR4
TX_NOT_EPT Flag
INxCSR5
FLUSH Bit
INxCSR6
AUTO_SET Bit
INxCSR7
Note 1: Write "1" only or read
Note 2: Write "0" only or read
Note 3: Read only
Note 4: Write only - Read "0"
Note 5: Refer to section 1.5.5 "Programming Notes" for this register
Address
0319 0321 0329 0331
16, 16, 16, 16
0 : Not ready
1 : Ready
0 : No FIFO underrun
1 : FIFO underrun has occured
0 : No action
1 : Stall IN Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
0 : Transmit FIFO is empty
1 : Transmit FIFO is not empty
0 : No action
1 : Flush the FIFO
0 : AUTO-SET disabled
1 : AUTO-SET enabled
Universal Serial Bus
When reset
00
16
Function R W
0 0
Note 1
0 0
Note 2
0 0
0 0
0 0
0 0
Note 3
0 0
Note 4
0 0