Usb Receive (Out) - Renesas M16C Series User Manual

M30240 Group

3.2.11 USB Receive (OUT)

The procedures for Endpoint 1-4 USB OUT transmission are shown in Figure 3.33 If isochronous
transfer is used, it is necessary to be aware that a USB Endpoint x OUT interrupt occurs even when
OVER_RUN is "1.
Confirm Data Reception in FIFO
b7
Note: Wait until bit becomes "1".
Reading Data Count
b7
Read Data from FIFO
b7
Note: Read the data count that is equal to the amount of received data.
Clearing OUT_PKT_RDY Flag
b7
Note: In the event the AUTO_CLR bit is "1", it automatically becomes "0". In the event of a double buffer zone, the
OUT_PKT_RDY flag remains "1" even after 1 packet data has been read because data remains in the OUT FIFO. In this
case, the OUT_PKT_RDY cannot be cleared to "0".
Figure 3.33: Procedures for receiving USB Transmission
Rev.1.00 Sep 24, 2003 Page 320 of 360
USB Endpoint x OUT Interrupt Processing Routine
Register Refuge Process
b0
USB Endpoint x OUT Control and Status Register
1
EPiOCS (i = 1-4)
OUT_PKT_RDY Bit (Note)
0 : Not ready
1 : Data packet ready
b0
USB Endpoint x OUT Write Count Register
EPiWC (i = 1-4)
Read Data Count
b0
USB Endpoint x FIFO Register
EPi (i = 1-4)
Unload Received Data
b0
USB Endpoint x OUT Control and Status Register
0
EPiOCS (i = 1-4)
OUT_PKT_RDY Bit (Note)
0 : Data packet read complete
Register Recover Processing
REIT Command Implementation
Universal Serial Bus
Address
031A 0322
16, 16,
032A 0332
16, 16
Address
031D 0325
16, 16,
032D 0335
16, 16
Address
0339 033A ,
16, 16
033B 033C
16, 16
Address
031A 0322
16, 16,
032A 0332
16, 16