Renesas M16C Series User Manual page 219

M30240 Group
2.5.1.2 Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the transfer
rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input from
the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively.
Examples of baud rate settings are shown in Table 2.17 .
Transfer rate formulas
When using internal clock:
When using external clock:
Table 2.18: Example of baud rate setting
Baud rate BRGs
(bps) count source
600 f8
1200 f8
2400 f8
4800 f1
9600 f1
14400 f1
19200 f1
28800 f1
31250 f1
Rev.1.00 Sep 24, 2003 Page 201 of 360
fi /16 (n+1)
fi = f , f , f
1 8 32
n = value in UARTi bit rate generator
f /16 (n+1)
EXT
f = input on CLKi pin
EXT
n = value in UARTi bit rate generator
System clock: 12 MHz
BRGs set value:n Actual time (bps)
155 (9B )
16
77 (4D )
16
38 (26 )
16
155 (9B )
16
77 (4D )
16
51 (33 )
16
38 (26 )
16
25 (19 )
16
23 (17 )
16
System clock: 7.3728 MHz
BRGs set value:n
95 (5F
601
16
47 (2F
1202
16
23 (17
2404
16
95 (5F
4807
16
47 (2F
9615
16
31 (1F
14423
16
23 (17
19230
16
15 (F
28846
16
31250 __
Clock-Asynchronous Serial I/O
Actual time (bps)
)
600
)
1200
)
2400
)
4800
)
9600
)
14400
)
19200
)
28800
__