Renesas M16C Series User Manual page 81

M30240 Group
DMAi source pointer (i = 0, 1)
(b23)
b7
DMAi destination pointer (i = 0, 1)
(b23)
b7
DMAi transfer counter (i = 0, 1)
(b15)
b7
Figure 1.56: DMAC register (3)
• Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses
and the software waits are inserted.
• Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd address-
es, there is one more source read cycle and destination write cycle than when the source and destination both
start at even addresses.
• Calculations
Any combination of even or odd transfer read and write addresses is possible. Table 1.16 show the number
of DMAC transfer cycles. Table 1.17 shows the corresponding coefficient values. Figure 1.57 shows an ex-
ample of the transfer cycle for a source read.
The number of DMAC transfer cycles can be calculated as follows:
Rev.1.00 Sep 24, 2003 Page 63 of 360
(b19) (b16)(b15) (b8)
b3 b0 b7 b0 b7
• Source pointer
Stores the source address
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
(b19) (b16) (b15) (b8)
b3 b0 b7 b0 b7
• Destination pointer
Stores the destination address
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
(b8)
b0 b7 b0
• Transfer counter
Set a value one less than the transfer count
Symbol Address
b0
SAR0 0022 to 0020
16
SAR1 0032 to 0030
16
Transfer count
Function
specification
00000 to FFFFF
16
b0
Symbol Address
DAR0 0026 to 0024
16
DAR1 0036 to 0034
16
Transfer count
Function
specification
00000 to FFFFF
16
Symbol Address
TCR0 0029 , 0028 Indeterminate
16 16
TCR1 0039 , 0038
16 16
Transfer count
Function
specification
0000 to FFFF
16
When reset
Indeterminate
16
Indeterminate
16
R W
16
When reset
Indeterminate
16
Indeterminate
16
R W
16
When reset
Indeterminate
R W
16
DMAC