Interrupts - Renesas M16C Series User Manual

M30240 Group

1.2.12 Interrupts

Table 1.9 and Table 1.10 show the interrupt sources and vector table addresses. When an interrupt is
received, the program is executed from the address shown by the respective interrupt vector.
The vector table addresses for the interrupts in Table 1.9 are fixed (interrupt vector addresses). These
interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupts in Table 1.10 are variable, being determined as relative to
the fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using
the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table
register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT
instruction to specify a software interrupt number, the program can be executed starting at the address
indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed
vector address and variable vector address. When the contents of FFFE4
"FF ", the program is executed from the address shown in the BRK instruction interrupt vector in the
16
variable vector address.
Specify the starting address of the interrupt program in the interrupt vector. Figure 1.15 shows the format
for specifying the address.
Table 1.9: Interrupt vectors with fixed addresses
Interrupt source
Undefined instruction
Overflow
BRK instruction
Address Match
Single Step (Note)
Watchdog timer
DBC (Note)
NMI
Reset
Note: Interrupts used for debugging purposes only
Figure 1.15: Format for specifying interrupt vector addresses
Rev.1.00 Sep 24, 2003 Page 28 of 360
Vector table addresses
Address(L) to Address(H)
FFFDC to FFFDF
16 16
FFFE0 to FFFE3
16 16
FFFE4 to FFFE7
16 16
FFFE8 to FFFEB
16 16
FFFEC to FFFEF
16 16
FFFF0 to FFF3
16 16
FFFF4 to FFFF7
16 16
FFFF8 to FFFFB
16 16
FFFFC to FFFFF
16 16
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Do not use
External interrupt by NMI pin
MSB LSB
Low address
Mid address
High
0 0 0 0
address
0 0 0 0 0 0 0 0
through FFFE7
16 16
Remarks
, program execution starts from
16
Interrupts
are all