Set Up After Usb Reset Signaling Detected; Set Up After Usb Suspend Detected - Renesas M16C Series User Manual

M30240 Group
RESET
FSE
LS
USBC4
USBC5
USBC7
Figure 1.118: PLL and DC-DC Converter Set Up Timing after Hardware Reset
1.5.1.3.1 Precautions after Software Reset
A software reset occurs after writing a '1' to bit '3' of the processor mode register 0 (address 0004
software reset, the contents of the internal RAM are preserved as well as all USB, DC-DC converter, and PLL
registers. If the PLL is used as the system clock source, it is important to note that after a software reset oc-
curs, any writes to the frequency synthesizer register will cause it to freeze. This can cause erratic device be-
havior. In order to avoid this, it is recommended that the following procedure be used:
• Prior to software reset, switch device clock source from 'fsyn to f(Xin)'. Please see the Frequency Synthe-
sizer specification for more details.
• After software reset using firmware, evaluate the condition of the synthesizer control register (FSC register,
address 03DC
enabled. If so, any setup routine that involves writing to the PLL registers should not be called. At this point,
the clock source can be changed back to fsyn.

1.5.1.4 Set up after USB Reset Signaling Detected

A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5
tection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a "1"
and the registers within the USB FCU being reset to their default values. Register USBC and the PLL
registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when
the USB Reset is detected.
No modifications to the frequency synthesizer or DC-DC converter configuration should be made in
the USB Function Interrupt routine. However, all USB FCU registers (addresses 300
be reconfigured to their pre-enumeration state.

1.5.1.5 Set up after USB Suspend Detected

A USB Suspend occurs if the USB FCU does not detect any bus activity on D+/D- for at least 3 ms.
Detection of a suspend results in bit 7 of USBIS2 and bit 0 of USBPM (SUSPEND) being set to a "1".
This causes bit 3 of SUSPIC to be set to a "1". Bit 7 of USBIS2 then needs to be cleared by writing a
"1" to the bit in order to allow a future suspend event.
The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in
the USB Suspend Interrupt routine (if the device is bus powered):
Rev.1.00 Sep 24, 2003 Page 133 of 360
, bit '0'). This bit is not effected by a software reset and can check to see if the PLL is still
16
Enable PLL
Wait 2 s
m
Enable DC-DC converter
Wait (C+1)
m
Frequency Synthesizer
s
Enable USB Clock
Wait at least 4 cycles of Φ
Enable USB FCU
16
to 33C
16 16
). During
µ
s. De-
) must