Renesas M16C Series User Manual page 58

M30240 Group
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSC0 = "0"), f
VCO
active (FSC0 = "1"), a lock status (LS = "1") indicates that f
LS and FSCO control bits in the FSC Control register are shown in Figure 1.27.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the
frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that
none of the registers be modified once the frequency synthesizer is enabled as it will cause the output
to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer
Clock Control register (FSCCR). See Figure 1.28.
Note: None of the registers must be written to once the frequency synthesizer is enabled and used as
the system clock source (FSCCR register, address 03DB
output of the PLL to freeze. Switch system back to f(X
Frequency Synthesizer Control Register
b7 b6 b5 b4 b3 b2
0 0
Figure 1.27: Frequency Synthesizer Control Register (FSC)
Frequency Synthesizer Clock Control Register
b7 b6 b5 b4 b3 b2
0 0 0 0 0 0 0
Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR)
Rev.1.00 Sep 24, 2003 Page 40 of 360
is held at either a high or low state. When the frequency synthesizer control bit is
b1 b0
Symbol
FSC
Bit symbol Bit name
Frequency Synthesizer Enable
FSE
VCO0
VCO Gain Control
VCO1
Reserved bit
CHG0
LPF Current Control
CHG1
Frequency Synthesizer
LS
Lock Status
Note : Recommended
b1 b0
Symbol
FSCCR
Bit symbol
Clock source selection
FSCCR0
Reserved
and f
SYN VCO
, bit "0" set to "1") because it will cause the
16
) and disable before modifying PLL registers.
IN
Address
03DC
16
0 : Disable
1 : Enabled
Bit 2 Bit 1
0 0:
0 1:
1 0:
1 1:
Must always be set to "0"
Bit 6 Bit 5
0 0:
0 1:
1 0:
1 1:
0: Unlocked
1: Locked
Address
03DB
16
Bit name
0 : X
IN
1 : fsyn
Must always be set to "0"
Frequency Synthesizer Circuit
are the correct frequency. The
When reset
60
16
Function
Lowest Gain (Note)
Low Gain
High Gain
Highest Gain
Disabled
Low Current
Intermediate Current (Note)
High Current
When reset
00
16
Function
R W
R W