Renesas M16C Series User Manual page 112

M30240 Group
Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
CTSi
TxDi
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = "1".
Example of transmit timing when transfer data are 9 bits long (parity enabled, two stop bits)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = "0".
Figure 1.89: Typical transmit timings in UART mode
Rev.1.00 Sep 24, 2003 Page 94 of 360
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to "L".
Tc
"1"
"0"
Data is set in UARTi transmit buffer register.
"1"
"0"
"H"
"L"
Start
bit
ST D D
D D D D
0 3
1 2 4 5
"1"
"0"
"1"
"0"
Tc
"1"
Data is set in UARTi transmit buffer register
"0"
"1"
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
ST D D D D D D
0 1 2 3 4 5
"1"
"0"
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Transferred from UARTi transmit buffer register to UARTi transmit register
Stopped pulsing because transmit enable bit = "0"
Parity Stop
bit bit
D P SP ST D D
D D D
7 0 3
6 1 2
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
f : frequency of BRGi count source (external clock)
EXT
n : value set to BRGi
Stop Stop
bit bit
D D D SP SP ST D D D D D
6 7 8 0 1 2 3
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of BRGi count source (f
f : frequency of BRGi count source (external clock)
EXT
n : value set to BRGi
UART0 to UART2
ST D
D D
D D D P SP 0
7
4 5 6
, f , f )
1 8 32
D D D D SPSP ST D D
4 5 6 7 8 0 1
EXT
1 , f 8 , f 32 )
1