Renesas M16C Series User Manual page 265

M30240 Group
Table 2.34: Variation of successive comparison register and V
(10-bit mode)
A-D converter stopped
1st comparison
2nd comparison
3rd comparison
10th comparison
Conversion complete
Result of A-D conversion
3FF
16
3FE
16
003
16
002
16
001
16
000
16
V
0
1024
V
REF
x 0.5
1024
Figure 2.93: Theoretical A-D conversion characteristics (10-bit mode)
Rev.1.00 Sep 24, 2003 Page 247 of 360
Successive approximation register
b9
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
n9
1st comparison result
1 0 0 0 0 0 0 0
n9 n8
2nd comparison result
n9 n8 n7 n6 n5 n4 n3 n2 n1
n9 n8 n7 n6 n5 n4 n3 n2 n1 n0
This data transfers to bit 0 and
bit 9 of A-D register
Theoretical A-D
conversion characteristic
V V
REF REF REF
x 1 x 2
1024 1024
while A-D conversion is in progress
REF
b0
V
REF
[V]
2
V V
REF REF
-
[V]
2 2048
V V V
REF REF
-
+
2 4 2048
V V
V
REF REF
+ +
2 4
V V V
REF REF
+ +
1
2 4
Ideal A-D conversion
characteristic
V V x 1022 V
REF REF
x 3 x 1021
1024 1024
A-D Converter
V change
REF
n9=1 + V
REF
4
REF
[V]
n9=0 - V
REF
4
n8=1 + V
V
REF
REF REF
-
[V]
8
8 2048
n8=0 - V
REF
8
V V
REF REF REF
+
+ -
[V]
8
1024 2048
REF
V
x 1023
REF
1024
Analog input voltage