Frequency Divider - Renesas M16C Series User Manual

M30240 Group

3.1.4.5 Frequency Divider

Clock f is a divided down version of f
SYN
register (FSD). When the Frequency Synthesizer Divider register is set to 255, division is disabled and
f = f . Table 3.4 shows some examples of how the frequency synthesizer division register is set.
SYN VCO
f = f / 2(m+1) m: FSD value
SYN VCO
Note 1: Set f to 12MHz or lower.
SYN
Table 3.4: Example of Setting the Frequency Synthesizer Divide Register (FSD)
fVCO
48.00 MHz
48.00 MHz
Rev.1.00 Sep 24, 2003 Page 292 of 360
. fsyn is generated via the Frequency Synthesizer Divide
VCO
FSD
Decimal List
1
127
Hexadecimal List
01
16
7F
16
Frequency Synthesizer
fSYN
12.00 MHz
187.50 MHz