Dmac; Overview - Renesas M16C Series User Manual

M30240 Group

2.7 DMAC

2.7.1 Overview

The DMAC (Direct Memory Access Controller) transfers one data item held in the source address to the
destination address every time a transfer request is generated. This transfer is done without using the
CPU. The following is a DMAC overview.
2.7.1.1 Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of 20
bits, so that each can cover a space of 1M bytes. After a transfer of one bit of data is completed, the
address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The relationship between the source and destination locations are as
follows:
(a) A fixed address from any SFR, ROM or RAM address;
(b) Any SFR, ROM or RAM address from a fixed address
(c) A fixed address from another fixed address
2.7.1.2 The number of bits of data transferred
The number of bits of data indicated by the transfer counter are transferred. If a 16-bit transfer is
selected, up to 128 K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt request occurs when the transfer counter overflows.
2.7.1.3 DMA transfer factor
The DMA transfer factor can be selected from the following 19 factors: falling edge of INT0/INT1 pin,
Timer A0 interrupt request through Timer A4 interrupt request, Timer B0 interrupt request, Timer B1
interrupt request, UART0 transmission interrupt request, UART0 reception interrupt request, UART1
transmission/UART1 reception interrupt request, UART2 transmission interrupt request, UART2
reception interrupt request, USB0 interrupt request, USB1 interrupt request, A-D conversion interrupt
request, and a software trigger.
When a software trigger is selected, a DMA transfer is generated by writing "1" to the software DMA
interrupt request bit. When any other factor is selected, the DMA transfer is generated by generating the
corresponding interrupt request.
2.7.1.4 Channel priority
If a DMA0 transfer request and a DMA1 transfer request occur simultaneously, priority is given to DMA0.
2.7.1.5 Writing to a register
When writing to the source register or the destination register with the DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to a
register with a fixed address when the DMA enable bit is set to "1". The contents of the register with
'forward direction' selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to at anytime.
2.7.1.6 Reading to a register
The reload register can be read from at anytime.
Rev.1.00 Sep 24, 2003 Page 255 of 360
DMAC