Related Registers - Renesas M16C Series User Manual

M30240 Group
sequence.
When an interrupt is generated in stop mode, CM10 becomes "0" and stop mode is cleared.
Starting oscillation and supplying Internal clock Φ executes the interrupt sequence as follows:
In the interrupt sequence, the processor carries out the following in the sequence given:
(a) The CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 00000 . The interrupt request bit of the interrupt written in address 00000
16
to "0".
(b) Saves the content of the flag register (FLG) as it was immediately before the start of the interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment flag
(U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers
32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
(g) After the interrupt sequence is completed, the processor resumes executing instructions from the
first address of the interrupt routine.
Note: This register cannot be utilized by the user.
Figure 2.125 shows the sequence of returning from stop mode.
Internal clock Φ
Address bus
Data bus
RD
WR
INTi
Figure 2.125: Sequence of returning from stop mode

2.12.1.6 Related registers

Figure 2.126 shows the memory map of power control-related registers, and Figure 2.127 shows power
control-related registers.
Figure 2.126: Memory map of power control related registers
Rev.1.00 Sep 24, 2003 Page 277 of 360
Writing "1" to CM10
Operated by divided-by-8 mode
(all clock stop control bit)
Address
00000
information
Stop mode Oscillation start-up
0006 System clock control register 0 (CM0)
16
0007 System clock control register 1 (CM1)
16
Indeterminate SP-2 SP-4
SP-2
Interrupt
Indeterminate
contents
Indeterminate
Interrupt sequence approximately 20 cycle (13.3 µ s)
(Single-chip mode, f(X ) = 12MHz)
IN
Power Control
will then be set
16
vec vec+2 PC
SP-4 vec vec+2
contents contents contents