Renesas M16C Series User Manual page 237

M30240 Group
Example of wiring
Example of operation
(1) Transmission enabled
Transfer clock
"1"
Transmit
enable bit (TE)
"0"
"1"
Transmit buffer
empty flag (Tl)
"0"
T D (Note 2)
X 2
R D (Note 2)
X 2
Signal line level
(Note 2)
Transmit buffer
"1"
empty flag (Tl)
"0"
"1"
Transmit
interrupt request
"0"
bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = "1".
Note 1: The transmit is started with overflow timing of BRG after writing in a value at the transmit buffer in the timing shown.
Note 2: TxD2 and RxD2 are wire connected as shown in the diagram and should become the same signal but the output signals
become complex so they are shown separately. Also, the signal level resulting from connecting the TxD2 and RxD2 is shown as a
signal line level.
Figure 2.68: Operation timing of transmission in UART mode (compliant with SIM interface)
Rev.1.00 Sep 24, 2003 Page 219 of 360
Microcomputer
TxD
2
RxD
2
(2) Start transmission
Tc
Data is set in UART2 transmit buffer register
Transferred from UART2 transmit buffer register to UART2 transmit register
Parity
Start
bit bit
ST D D D D D D D P
D
0 1 2 3 4 5 6 7
ST D D D D D D D D P
0 1 2 3 4 5 6 7
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Clock-Asynchronous Serial I/O
SIM card
(3) Confirm stop bit
(4) Start transmission
(Note 1)
Stop
bit
SP ST D D D D D D
0 1 2 3 4
Since a parity error occurred, the
"L" level returns from TxD
SP ST D D D D D D
0 1 2 3 4
Detects the level
using an interrupt
routine
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
(5) Dispose
parity error
D P
D
5 6 7
SP
2
SP
D D P
5 6 7
Detects the level
using an interrupt
routine