Renesas M16C Series User Manual page 325

M30240 Group
• OVER_RUN Flag
This bit is used during isochronous transfers only.
The USB Function Control Unit sets this bit to "1" when a FIFO overrun is detected. When interrupts
are enabled, a USB overrun/underrun interrupt occurs. Write a "0" to clear this bit.
• SEND_STALL Bit
This bit should be set to "1" when there is a STALL condition. The USB Function Control Unit sends
a STALL handshake signal to the host CPU while this bit is set to "1". Write a "0" to clear this bit.
• ISO/TOGGLE_INIT Bit
This bit performs the double function of an ISO bit and a Toggle bit.
• ISO bit
When the endpoint is to be used for isochronous transfer, this bit should be set to "1". If the ISO bit is set to
"1", the PID of the data that is transmitted from the host is accepted as either DATA0 or DATA1. This bit should
be fixed at "1" while the isochronous transfer is being used.
• TOGGLE-INIT bit
The TOGGLE_INIT bit is set to "1" to initialize the data toggle sequence of the endpoint (reset the next data
packet to DATA0). This bit should be set to "1" and then it should be cleared to "0" only when the endpoint is
being configured.
• FORCE_STALL Flag
The USB Function Control unit sets this bit to a "1" when the host sends out a larger data packet than
the MaxP size. It also sends a STALL handshake to the host CPU while this bit is "1." Write a "0" to
clear this bit.
• DATA_ERR Flag
This flag is used only when an isochronous transfer is being used. The USB Function Control Unit sets
this bit to a "1" when a CRC or bit stuffing error is detected. Write a "0" to clear this bit.
• FLUSH Bit
This bit should be set to "1" to flush the data within the OUT FIFO. When their is one packet in the
FIFO, a flush empties the FIFO. When there are two packets in the FIFO, the older packet is flushed
from the FIFO.
• AUTO_CLR Bit
When this bit is "1," the OUT_PKT_RDY flag is automatically cleared to "0" after the number of data
bytes equal to the MaxP are unloaded from the OUT_FIFO. If a short packet is unloaded from the
OUT_FIFO, the CPU must clear OUT_PKT_RDY.
Figure 3.22 shows the structure of the USB Endpoint x OUT Control/Status Register
Rev.1.00 Sep 24, 2003 Page 307 of 360
Universal Serial Bus