Renesas M16C Series User Manual page 41

M30240 Group
RESET
Software reset
NMI
Interrupt request
level judgment
output
WAIT instruction
CM0i :
CM1i :
FSCCRi: Bit i at address 03DB
Figure 1.12: Clock-generating circuit
1.2.6.2 Clocks generated by the clock-generating circuit.
Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the internal clock Φ.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the X
pin can be reduced using the X
the drive capacity of the X
to stop mode and after a reset.
Internal clock Φ
The internal clock Φ is the clock that drives the CPU, and is either the main clock or is derived by di-
viding the main clock by 2, 4, 8, or 16. The internal clock Φ is derived by dividing the main clock by 8
after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 0006
Peripheral Function clock
• f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral func-
tion clock stop bit (bit 2 at 0006
Rev.1.00 Sep 24, 2003 Page 23 of 360
X
IN
Main clock
FSCCR0=1
FSCCR0=0
CM10 "1"
S Q
Write signal
R
S Q
R
Bit i at address 0006
16
Bit i at address 0007
16
16
- X ) drive capacity select bit (bit 5 at address 0007
IN OUT
pin reduces the power dissipation. This bit defaults to "1" when shifting
OUT
) to "1" and then executing a WAIT instruction.
16
X
OUT
Frequency
Synthesizer
fsyn
Circuit
a
CM02
1/2 1/2
a
CM06=0
CM17,CM16=10
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
Clock-Generating Circuit
f
usb (48MHz)
f
AD
f SIO2
1
f
1
f SIO2
8
f
8
f SIO2
32
f
32
b c
d
Divider
BCLK
c
b
1/2 1/2 1/2
CM06=0
CM17,CM16=11
CM06=1
Details of divider
). Reducing
16
) is set to "1".
16
φ
d
OUT