Renesas M16C Series User Manual page 355

M30240 Group
The following are conditions under which an interrupt is accepted:
• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL
Table 4.4: Settings of interrupt priority levels
Interrupt priority level select bit
b2 b1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 4.5: Interrupt levels enabled according to the contents of the IPL
IPL
IPL IPL
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt
in the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect on the instruction that
is executed 2 clock cycles after the last clock cycle involved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect
on the instruction that is executed 3 cycles after the last clock cycle involved in the instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect on the instruction that is executed 2 clock cycles after the last clock cycle involved in the in-
struction used.
Rev.1.00 Sep 24, 2003 Page 337 of 360
Interrupt priority level
b0
0 Level 0 (interrupt disabled)
1 Level 1
0 Level 2
1 Level 3
0 Level 4
1 Level 5
0 Level 6
1 Level 7
IPL
0
0 Interrupt levels 1 and above are enabled
1 Interrupt levels 2 and above are enabled
0 Interrupt levels 3 and above are enabled
1 Interrupt levels 4 and above are enabled
0 Interrupt levels 5 and above are enabled
1 Interrupt levels 6 and above are enabled
0 Interrupt levels 7 and above are enabled
1 All maskable interrupts are disabled
Enabled interrupt priority levels
Overview of Interrupts
Priority order
Low
High