Renesas M16C Series User Manual page 321

M30240 Group
• Receive an illegal data toggle during a STATUS stage,
• Receive an illegal data toggle during a SETUP stage,
• Host requests more data than specified during the SETUP stage (receive an IN token when the
DATA_END is set),
• Host sends more data then specified during the SETUP stage (receive an OUT token when the
DATA_END is set),
• Receive larger data packet than the maximum packet (MaxP) size.
All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a
STALL handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the
device sends ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A
STALL handshake caused by the above listed conditions lasts for one transaction and terminates the
ongoing control transfer. Any packet after the STALL handshake will be seen as the beginning of a
new control transfer.
The CPU writes a "0" to clear the FORCE_STALL status bit.
• SETUP_END Flag
This becomes "1" when processing is interrupted in mid course prior to the end of the transfer of the
data size set during the control transfer and data phase processing. This bit should be cleared to "0"
by writing "1" to the SERVICED_SETUP_END bit.Once the CPU detects the SETUP_END bit as set,
it should stop accessing the FIFO to service the previous setup transaction.
If this bit should become "1" and the OUT_PKT_RDY flag simultaneously becomes "1", that would in-
dicate that the setup processing that was established earlier has been completed and that there is a
new SETUP token inside the FIFO.
• SERVICED_OUT_PKT_RDY Bit
The OUT_PKT_RDY is cleared to "0" when this bit is set to "1".
• SERVICED_SETUP_END Bit
The SETUP_END bit is cleared to "0" when this bit is set to "1".
Figure 3.17 shows the structure of the USB Endpoint 0 Control/Status Register
U S B E n d p o in t 0 C o n tro l a n d S ta tu s R e g is te r (N o te 5 )
b 7 b 6 b 5 b4 b 3
Figure 3.17: USB Endpoint 0 Control/Status Register (EP0CS)
Rev.1.00 Sep 24, 2003 Page 303 of 360
b 2 b 1 b 0
S y m b o l
E P 0 C S
B it S y m b o l
E P 0 C S R 0
O U T _ P K T _ R D Y F la g
E P 0 C S R 1
IN _ P K T _ R D Y B it
E P 0 C S R 2 S E N D _ S T A L L B it
E P 0 C S R 3
D A T A _ E N D B it
E P 0 C S R 4
F O R C E _ S T A L L F la g (N o te 1 )
E P 0 C S R 5 S E T U P _ E N D F la g
E P 0 C S R 6
S E R V IC E D _ O U T _ P K T _ R D Y B it
E P 0 C S R 7 S E R V IC E D _ S E T U P _ E N D B it
N o te 1 : R e a d o n ly
N o te 2 : W rite " 1 " o n ly o r R e a d
N o te 3 : W rite " 0 " o n ly o r R e a d
N o te 4 : W rite o n ly - R e a d "0 "
N o te 5 : R e fe r to P ro g ra m m in g N o te s in C h a p te r 1 , S e c tio n 5 .5
A d d re s s W h e n re s e t
0 3 1 1
1 6
B it N a m e F u n c tio n
0 : N o t re a d y
1 : R e a d y
0 : N o t re a d y
1 : R e a d y
0 : N o a c tio n
1 : S ta ll E n d p o in t 0 b y C P U
0 : N o a c tio n
1 : L a s t p a c k e t tra n s fe rre d to /fro m F IF O
0 : N o a c tio n
1 : S ta ll E n d p o in t 0 b y U S B F C U
0 : N o a c tio n
1 : C o n tro l tra n s fe r e n d e d b e fo re s p e c ific
d a ta le n g th tra n s fe rre d d u rin g d a ta p h a s e
0 : N o c h a n g e
1 : C le a r O U T _ P K T _ R D Y b it
0 : N o c h a n g e
1 : C le a r S E T U P _ E N D b it
Universal Serial Bus
0 0
1 6
R W
O O
N o te 1
O O
N o te 2
O O
O O
N o te 2
O O
N o te 3
O O
N o te 1
O O
N o te 4
O O
N o te 4