Renesas M16C Series User Manual page 111

M30240 Group
Figure 1.88 and Figure 1.89 show the typical UART mode transmit and receive timing diagrams.
Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit)
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Receive interrupt
request bit
Figure 1.88: Typical receive timing in UART mode
Rev.1.00 Sep 24, 2003 Page 93 of 360
"1"
"0"
Start bit
Sampled "L"
Reception triggered when transfer clock
"1"
is generated by falling edge of start bit
"0"
"H"
"L"
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
.......
.......
D D D
1 ....... 7
0
Receive data taken in
Transferred from UARTi receive register to
UARTi receive buffer register
UART0 to UART2
Stop bit