Frequency Synthesizer Circuit; Prescaler - Renesas M16C Series User Manual

M30240 Group

1.2.17 Frequency Synthesizer Circuit

The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock f
that are both a multiple of the external input reference clock f(X
in Figure 1.23.
f(X )
IN
03DE
Figure 1.23: Frequency Synthesizer Circuit
The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider
macro, and five registers, namely FSP, FSM, FSC, FSD, and FSCCR. Clock f(X
using FSP to generate f
using FSD to produce the clock f
and sent out of the frequency synthesizer block as signal f

1.2.17.1 Prescaler

Clock f is a divided down version of clock f(X
PIN
and the clock input to the prescaler f(X
• f = f(X ) / 2(n+1) where n is a decimal number between 0 and 254.
PIN IN
Setting FSP to 255 disables the prescaler and f
• Note: f(X ) frequency below 1 MHz is not recommended.
IN
MSB
7
Figure 1.24: Frequency Synthesizer Prescaler Register (FSP)
Rev.1.00 Sep 24, 2003 Page 38 of 360
Frequency
f
PIN
Prescaler
Multiplier
FSP FSM
03DD
. f is multiplied using FSM to generate an f
PIN PIN
. The f
SYN
) is as follows:
IN
Bit 7 Bit 6 Bit 5
2
f
PIN
Dec(n)
12 MHz 255
1 MHz 5
2 MHz 2
3 MHz 1
6 MHz 0
f(X )/2(n+1) = f
IN
). A block diagram of the circuit is shown
IN
EN
USBC5
f
Frequency
VCO
Divider
LS
8 Bit
FSC FSD
03DC 03DF
clock is optimized for 48 MHz operation and is buffered
VCO
. This signal is used by the USB block.
USB
) (see Figure 1.24). The relationship between f
IN
= f(X ).
PIN IN
Bit 2
Bit 4 Bit 3
FSP
f(Xin)
Hex(n)
FF 12.00 MHz
05 12.00 MHz
02 12.00 MHz
01 12.00 MHz
00 12.00 MHz
PIN
Frequency Synthesizer Circuit
f
USB
f
SYN
FSCCR0
FSCCR
03DB
Data Bus
) is prescaled down
IN
clock which is then divided
VCO
Address: 03DE
LSB
Bit 1 Bit 0
0
Access: R/W
Reset:
SYN
PIN
16
FF
16