Usb Reset Interrupt; Usb Resume Interrupt - Renesas M16C Series User Manual

M30240 Group
0.0.0.0.1 Endpoint x IN Interrupt and Endpoint x OUT Interrupt
When any USB Endpoint x IN interrupt status flags or USB Endpoint x OUT interrupt status flags of
the USB interrupt status register 1 (USBIS1) and the USB interrupt status register 2 (USBIS2) are set
to "1," a USB Function interrupt request occurs. Endpoints 1-4 have 2 interrupt status bits (IN and
OUT) and Endpoint 0 has 1 bit. Each interrupt status flag is set to "1" under the following conditions:
• The USB Endpoint 0 interrupt status flag (INTST0) (When Endpoint 0 is used)
• 1 data packet received successfully at Endpoint 0
• 1 data packet transmitted successfully from Endpoint 0
• DATA_END bit is cleared by the USB FCU
• FORCE_STALL flag is set by the USB FCU
• SETUP_END flag is set by the USB FCU
• The USB Endpoint x (x=1-4) IN interrupt status flag (INTST 2, 4, 6, 8) (When Endpoint 1-4 is used)
• 1 data packet transmitted successfully from Endpoint x (x=1-4)
• UNDER_RUN flag is set by USB FCU
• The USB Endpoint x (x =1-4) OUT interrupt status flag (INTST 3, 5, 7, 9) (When Endpoint 1-4 is used)
• 1 data packet received successfully at Endpoint x (x=1-4)
• OVER_RUN is set by USB FCU
• FORCE_STALL is set by USB FCU
0.0.0.0.2 Overrun/Underrun Interrupt
This interrupt is valid only when an isochronous transfer is used. Endpoints 1-4 can be used for isochronous trans-
fers.
When the USB overrun/underrun interrupt status flag in the USB interrupt status register 2 (USBIS2
is "1," an interrupt request occurs. The USB overrun/underrun interrupt occurs under the following conditions:
• Overrun
• Occurs when the host sends an OUT packet and two data packets are already in the OUT FIFO.
• Underrun
• Occurs when the host sends an IN packet but not data is present in the IN FIFO

3.2.7.2 USB Reset Interrupt

An interrupt request occurs when the interrupt status flag of the USB Reset Interrupt Control register
(RSTIC) is "1." The USB reset interrupt status flag is set to "1" when the USB Function Control Unit
receives a USB reset signal (when a 2.5ms interval SE0 is detected on the D+/D- line).
At time of USB reset, the registers (Addresses 0300
transmitted again from the host CPU, the initial settings for each of the endpoints should set.
Note 1: The USB control register (USBC) and the frequency synthesizer related registers are not af-
fected by a USB reset.

3.2.7.3 USB Resume Interrupt

An interrupt request occurs when the interrupt status flag of the USB Resume Interrupt Control register
(RSMIC) is "1."
The USB Resume Interrupt Status flag is set to "1" when the USB function control unit receives a re-
sume signal during suspend mode.
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