Set Up After Usb Resume Signaling Detected; Pll Lock Bit - Renesas M16C Series User Manual

M30240 Group
• Change the DC-DC converter from high current mode to low current mode by setting USBC3 (bit 3
of the USBC) to a "1"
• Disable the USB clock by setting USBC5 (bit 5 of USBC) to a "0". Once the USB clock is disabled,
registers internal to the USB FCU should not be written to. This includes all USB SFRs from address
0300
to 033C
16
• Perform other tasks to reduce total current to below 500µA.
• Disable the PLL by setting FSE (bit 0 of FSC) to a "0".
• Make sure the I-FLAG is set to "1".
• Stop the system clock by setting CM10 (bit 0 of CM1) to a "1". Make sure to first enable writing to the
system clock control register by setting PRCO (bit 0 of PRCR) to "1'. Also, make sure to enable the
USB Resume Interrupt (RSMIC register) and clear or execute any pending interrupts prior to stop-
ping the clock so the MCU can wake up once resume signaling is detected. If the clock is stopped
using an interrupt routine, make sure to set the priority of the Resume Interrupt (RSMIC) higher than
the current interrupt.
• Note that no action may be necessary if the device is self powered.

1.5.1.6 Set up after USB Resume Signaling Detected

A resume occurs when the USB FCU is in the suspend state and detects a non-idle signaling on D+/
D-. Detection of a resume results in bit 6 of USBIS2 and bit 1 of USBPM (RESUME) being set to a "1".
This causes bit 3 of RSMIC to also be set to "1". If the MCU was in the stop state prior to the detection
of the resume, the USB Resume Interrupt request will cause the MCU to wake up from the stop state.
Bit 6 of USBIS2 needs to be cleared (by writing a "1" to the bit) in order to allow a future resume event.
See section 2.9 "Stop Mode" for details on waking up from the stop state.
The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in
the USB Resume Interrupt routine (if the device is bus powered):
• Re-enable the PLL for 48MHz f(VCO) by setting FSE (bit 0 of the FSC) to a "1", then wait for 2 ms.
• Wait for 2 ms.
• Check the lock status bit (LS, bit 7 of FSC).
• If the bit is a "1", continue.
• If the bit is a "0", wait 0.1
• Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1".
• Wait for a minimum of 4 cycles.
• Change the DC-DC converter from low current mode to high current mode by setting USBC3 (bit 3
of the USBC) to a "0".
• Enable other blocks as necessary.
Registers internal to the USB FCU should not be written to until the USB clock is re-enabled. This in-
cludes all USB SFRs from address 0300
Note that the configuration changes described above may not need to be made if the MCU was not
placed in a suspend state as described in section 5.1.2.3 Set up after USB Suspend Detected.

1.5.1.7 PLL Lock Bit

The PLL lock bit is used to indicate when the PLL is first locked. Accordingly, after the PLL is enabled
and it has been given 2.0 ms to stabilize, the lock bit status should be checked. Once the lock bit is
HIGH, the USB check should be enabled. After this stage, the lock bit is no longer valid and should
not be monitored, unless the PLL is re-enabled.
Rev.1.00 Sep 24, 2003 Page 134 of 360
. It does not include USBC or FSC.
16
ms
longer and then re-check the bit.
16
to 033C . It does not include USBC or FSC.
16
Frequency Synthesizer