Hardware Interrupts - Renesas M16C Series User Manual

M30240 Group
The stack pointer (SP), used for the INT interrupt, is dependent on which software interrupt number is
involved.
When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to "0" and the
processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the
received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not
change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the
case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and
undefined instruction interrupts.

4.1.1.2 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an "L" is input to the RESET pin.
• NMI interrupt
An NMI interrupt occurs if an "L" is input to the P85/ NMI pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag)
set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by the ad-
dress match interrupt register is executed with the address match interrupt enable bit set to "1".
If an address other than the first address of the instruction in the address match interrupt register is set, no
address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral
functions are dependent on classes of products, so the interrupt factors too are dependent on classes
of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts the DMA generates.
• Key-input interrupt
A key-input interrupt occurs if any pin of Port 0 or Port 1 is configured as an input and a falling edge is input
to that pin.
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Overview of Interrupts