Wait Mode Set-Up - Renesas M16C Series User Manual
16-bit single-chip microcomputer
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2.12.3 Wait Mode Set-Up
Settings and operation for entering wait mode are described here.
(1) Enable the interrupt used that is to be used for returning from wait mode.
(2) Set the interrupt enable flag (I flag) to "1".
(3) Clear the protection register.
(4) Change the content of the system clock control register.
(5) Execute the WAIT instruction.
Figure 1.129 shows the set up for the Wait mode.
(1) Setting interrupt to cancel stop mode
Interrupt control register
BCNIC
KUPIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 1)
SUSPIC
RSMIC
RSTIC
USBFIC
b7
(2) Interrupt enable flag (I flag)
(3) Canceling protect
b7
(4) Control of CPU clock
b7
0
0 0 0
Note: When switching the system clock, it is necessary
to wait for the oscillation to stabilize.
(5) WAIT instruction
Figure 2.129: Set-up for Wait mode
Rev.1.00 Sep 24, 2003 Page 280 of 360
[Address 004A
]
16
[Address 004D
]
16
[Address 0051
, 0053
, 004F
]
16
16
16
[Address 0052
, 0054
, 0050
]
16
16
16
[Address 0055
to 0059
]
16
16
[Address 005A
to 005B
]
16
16
[Address 0044
]
16
[Address 0046
]
16
[Address 005C
]
16
[Address 005F
]
16
b0
b7
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
WAIT instruction is executed.
"1"
b0
Protect register [Address 000A
]
16
1
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 0006
and 0007
)
16
16
1 : Write-enabled
b0
System clock control register 1
[Address 0007
] CM1
16
Reserved bit
Must be set to "0"
Main clock division select bit
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Wait mode
SOFIC
[Address 0047
[Address 005D
INTiIC (i=0 to 1)
b0
0
Interrupt priority level select bit
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Reserved bit
Must be set to "0"
b7
b0
System clock control register 0
[Address 0006
0
0 0
1
WAIT peripheral function clock stop bit
0 : Do not stop f
1 : Stop f
, f
1
8
Reserved bit.
Must be set to "1"
Reserved bit. Must be set to "0"
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
Reserved bit. Must be set to "0'
Power Control
]
16
to 005E
]
16
16
] CM0
16
, f
, f
in wait mode
1
8
32
, f
in wait mode
32
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