Renesas M16C Series User Manual page 116

M30240 Group
1.2.23.3.1 Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D
the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission
completion interrupt changes to the detection timing of a parity error signal. Figure 1.93 shows the output tim-
ing of the parity error signal.
• LSB first
Transfer
clock
RxD
TxD
Receive
complete flag
Figure 1.93: Output timing of the parity error signal
1.2.23.3.2 Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the
direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output
from TxD2.
Figure 1.94 shows the SIM interface format.
Transfer
clock
TxD
2
(direct)
TxD
2
(inverse)
Figure 1.94: SIM interface format
Figure 1.95 shows the example of connecting the SIM interface with TxD2 and RxD2.
Figure 1.95: Connecting the SIM interface
Rev.1.00 Sep 24, 2003 Page 98 of 360
"H"
"L"
"H"
2 ST D0 D1
"L"
"H"
2
"L"
"1"
"0"
D0 D1 D2
D7 D6 D5
Microcomputer
TxD
2
RxD
2
) assigned "1", you can output an "L" level from
16
D2 D3 D4 D5 D6 D7
Hi-Z
ST : Start bit
P : Even Parity
SP: Stop bit
D3 D4 D5 D6 D7
D4 D3 D2 D1 D0
SIM card
UART0 to UART2
P SP
P
P
P : Even parity