Renesas M16C Series User Manual page 241

M30240 Group
Example of wiring
Example of operation
(1) Reception enabled
Transfer clock
"1"
Receive enable
bit
(RE)
"0"
R D (Note)
X 2
T D (Note)
X 2
Signal line level
(Note)
Receive "1"
complete flag
(RI)
"0"
"1"
Receive interrupt
request bit
(IR)
"0"
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = "1".
Note: TxD and RxD
2
become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,
the signal level resulting from connecting TxD
Figure 2.71: Operation of reception in UART mode (compliant with SIM interface)
Rev.1.00 Sep 24, 2003 Page 223 of 360
Microcomputer
TxD
2
RxD
2
(2) Start reception
Tc
Parity
Start
bit
bit
ST D D D D D D D
D
0 1 2 3 4 5 7
6
ST D D D
D D D D D
0 3 7
1 2 4 5 6
Cleared to "0" when interrupt request is accepted, or cleared by software
are connected in the manner of wired OR as shown in the connection diagram. So TxD
2
and RxD
2
SIM card
(3) Receiving is completed
(4) Data is read
Stop
bit
P ST D D D D
SP
0 1 2 3
Since a parity error occurred, the
"L" level returns from TxD
ST D D
P SP D D
0 3
1 2
Read to receive buffer
Tc = 16 (n + 1) / fi
fi : value set to BRG2 count source (f1, f8, f32)
n: value set to BRG2
is shown as a signal line level.
2
Clock-Asynchronous Serial I/O
(5) Parity error occurred
SP
D D D P
D
4 5 7
6
2
SP
D
D D D P
7
4 5 6
Read to receive buffer
and RxD ought to
2 2