Performance Outline - Renesas M16C Series User Manual

M30240 Group

1.1.5 Performance outline

Table 1.1 is a performance outline of the M30240 group.
Table 1.1: Performance outline of M30240 group
Number of basic instructions
Shortest instruction execution time
Memory capacity
I/O port
Input port
Multifunction Timer
General purpose Timer
Serial I/O
A-D converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock-generating circuit
Supply voltage (typical)
Power consumption (typical)
I/O characteristics
Operating temperature
Device configuration
Package
Rev.1.00 Sep 24, 2003 Page 5 of 360
Item
ROM
RAM
P0 to P3, P6,P7, P8
(except P85), P10
P85
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
UART0, UART1, UART2
I/O withstand voltage
Average output current
Performance
91 instructions
83ns (f(X ) =12MHz)
IN
(See Table 1.2: ROM capacity field)
8 bits x 7, 7 bits x 1
1 bit x 1
16 bits x 5
16 bits x 3
(UART or clock synchronous) x 3
10 bits x 8 channels
2 channels (trigger:19 sources)
CRC-CCITT
15 bits x 1 (with prescaler)
21 internal and 4 external sources, 4 software sources, 7 levels
Built-in clock generation circuit (built-in feedback resistor, and
external ceramic or quartz oscillator)
4.1 to 5.25V, (f(X )=12MHz, without software wait)
IN
250 mW, Vcc=5.0V, 12MHz
5V
5 mA available on ports P0, P1, P3,P6, P7
P8 ~P8 , P8 , P8 , P10
1 4 6 7
10 mA available on ports P2, P7
o
0 to 70 C
CMOS high performance silicon gate
80-pin plastic molded QFP
Performance outline
, P7 , P7 , P7
1 3 5 7
, P7 , P7 , P7 , P8
0 2 4 6 0
,