Usb Endpoint X Out Maxp Register; Usb Endpoint X Out Write Count Register - Renesas M16C Series User Manual

M30240 Group
USB Endpoint x OUT Control and Status Register (Note 3)
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Figure 3.22: USB Endpoint x OUT CSR

3.2.2.17 USB Endpoint x OUT MaxP Register

This register indicates the Maximum Packet size (MaxP) of Endpoint x (x=1-4) OUT packet. The MaxP
register should be set when the SET_DESCRIPTOR command is received from the host CPU. When
MaxP > half of the FIFO size, single buffer mode is selected. When MaxP <= half the FIFO size, double
buffer mode is selected.
Figure 3.23 shows the structure of the USB Endpoint x OUT MaxP Register
USB Endpoint x OUT MaxP Register
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Figure 3.23: USB Endpoint xOUT MaxP

3.2.2.18 USB Endpoint x OUT Write Count Register

This register contains the current number of bytes in the Endpoint x (x = 1-4) OUT FIFO. The USB
Function Control unit sets the value of this register after a data packet is completely received from the
host CPU. Refer to this register when the data is read from the OUT FIFO.
Figure 3.24 shows the structure of the USB Endpoint x(x = 1-4) OUT Write Count Register
USB Endpoint x OUT Write Count Register
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Figure 3.24: USB Endpoint x OUT WRT CNT Register
Rev.1.00 Sep 24, 2003 Page 308 of 360
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Symbol
EPiOCS (i=1-4)
Bit Symbol
OUTxCSR0
OUT_PKT_RDY Flag
OUTxCSR1
OVER_RUN Flag
OUTxCSR2 SEND_STALL Bit
OUTxCSR3
ISO Bit (Note 1)
OUTxCSR4
FORCE_STALL Flag
OUTxCSR5 DATA_ERR Flag
OUTxCSR6
FLUSH Bit
OUTxCSR7 AUTO_CLR Bit
Note 1: Write "0" only or Read
Note 2: Write only or Read
Note 3: Refer to Programming Notes in Chapter 1, Section 5.5
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Symbol
EPxOMP (x=1-4)
Bit Symbol
OMAXP0 to
OMAXP7
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Symbol
EPxWC (x=1-4)
Bit Symbol
W_CNT0 to
W_CNT7
Address
031A , 0322 , 032A , 0332
16 16 16 16
Bit Name Function
0: Not ready
1: Ready
0: No FIFO OVerrun
1: FIFO overrun occured
0: No action
1: Stall OUT Endpoint x by CPU
0: Select non-isochronous transfer
1: Select isochronous transfer
0: No action
1: Stall Endpoint x by USB FCU
0: No error
1: CRC or bit stuffing error received in ISO packet
0: No action
1: Flush FIFO
0: AUTO_CLR disabled
1: AUTO_CLR enabled
Address
031C , 0324 , 032C , 0334
16 16 16
Bit Name Function
For endpoints that support
Maximum packet size
smaller FIFO size, unused bits
(MAXP) of Endpoint x OUT
are not implemented. (Always
packet
write "0" to those bits.)
Address
031D , 0325 , 032D , 0335
16 16 16 16
Bit Name Function
Write count bit
Receive byte count
Universal Serial Bus
When reset
00
16
R W
O O
Note 1
O O
Note 1
O O
O O
O O
Note 1
O O
Note 1
O O
Note 2
O O
When reset
00
16
16
R W
O O
When reset
00
16
R W
O X