Renesas M16C Series User Manual page 206

M30240 Group
Setting UARTi transmit/receive mode register (i=0 to 2)
b7 b0
0 0 0 0 1
Must be fixed to "001"
Internal/external clock select bit
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Setting UARTi transmit/receive control register 0 (i=0 to 2)
b0
b7
0 0 0 0
Note: Set the corresponding port direction register to "0" .
Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1
b0
b7
0 0 0 0
UART0 transmit interrupt cause select bit
UART1 transmit interrupt cause select bit
Figure 2.46: Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
Rev.1.00 Sep 24, 2003 Page 188 of 360
UART0 transmit/receive mode register
[Address ]
U0MR 03A0
16
UART1 transmit/receive mode register
[Address ]
U1MR 03A8
16
0 : Internal clock
Must be "0" in clock synchronous I/O mode
UART0 transmit/receive control register 0
U0C0 [Address 03A4 ]
16
UART1 transmit/receive control register 0
U1C0 [Address 03AC ]
16
BRG count source select bit
b1 b0
0 0 : f is selected
1
0 1 : f is selected
8
1 0 : f is selected
32
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = "0")
0 : CTS function is selected (Note)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
CLK polarity select bit
0 : Transmission data is output at falling
edge of transfer clock and reception data is
input at rising edge
Transfer format select bit
0 : LSB first
UART transmit/receive control register 2
UCON [Address 03B0 ]
16
0 : Transmit buffer empty (Tl = 1)
0 : Transmit buffer empty (Tl = 1)
Valid when bit 5 = "1"
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
Reserved
Must always be "0"
Continued to the next page
Clock-Synchronous Serial I/O
b7 b0
UART2 transmit/receive mode register
0 0 0 0 1
[Address
U2MR
Must be fixed to "001"
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
T D, R D I/O polarity reverse bit
X X
Usually set to "0"
UART2 transmit/receive control register 0
b7 b0
U2C0 [Address
0 0 0 0
BRG count source select bit
b1 b0
0 0 : f is selected
1
0 1 : f is selected
8
1 0 : f is selected
32
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = "0")
0 : CTS function is selected (Note)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
CLK polarity select bit
0 : Transmission data is output at falling
edge of transfer clock and reception data
is input at rising edge
Transfer format select bit
0 : LSB first
UART2 transmit/receive control register 1
b7 b0
0 0
0
U2C1 [Address 037D
UART2 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Data logic select bit
0 : No reverse
Error signal output enable bit
Must be "0" in clock synchronous I/O
mode
]
0 3 7 8
1 6
]
037C
16
]
16